inteltool: refine GPIO and PMBASE/TCO printing on Ibex Peak/5 Series
Nicolas Reinecke was noticing that in my Lenovo T410s logs the GPIO*3 settings were missing. This led to some investigation and this patch, thanks! Change-Id: I7ba28aa00d10f988a7fe81e61d2e216b54a11006 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/7239 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Stefan Tauner
Nico Huber
parent
e69c6133c2
commit
b75a39a2fe
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@ -258,6 +258,44 @@ static const io_register_t pch_gpio_registers[] = {
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{ 0x78, 4, "RESERVED" },
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{ 0x7c, 4, "RESERVED" },
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};
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/* Default values for Ibex Peak desktop chipsets */
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static const gpio_default_t ip_pch_desktop_defaults[] = {
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{ 0x00, 0xf96ba1ff }, /* GPIO_USE_SEL */
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{ 0x04, 0xf6ff6eff }, /* GP_IO_SEL */
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{ 0x0c, 0x02fe0100 }, /* GP_LVL */
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{ 0x18, 0x00040000 }, /* GPO_BLINK */
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{ 0x1c, 0x00000000 }, /* GP_SER_BLINK */
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{ 0x28, 0x00000000 }, /* GP_NMI_EN + GPI_NMI_STS */
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{ 0x2c, 0x00000000 }, /* GP_INV */
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{ 0x30, 0x020300ff }, /* GPIO_USE_SEL2 */
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{ 0x34, 0x1f57fff4 }, /* GP_IO_SEL2 */
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{ 0x38, 0xa4aa0003 }, /* GP_LVL2 */
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{ 0x40, 0x00000100 }, /* GPIO_USE_SEL3 */
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{ 0x44, 0x00000f00 }, /* GP_IO_SEL3 */
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{ 0x48, 0x00000000 }, /* GP_LVL3 */
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{ 0x60, 0x01000000 }, /* GP_RST_SEL1 */
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{ 0x64, 0x00000000 }, /* GP_RST_SEL2 */
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{ 0x68, 0x00000000 }, /* GP_RST_SEL3 */
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};
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/* Default values for Ibex Peak mobile chipsets */
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static const gpio_default_t ip_pch_mobile_defaults[] = {
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{ 0x00, 0xf96ba1ff }, /* GPIO_USE_SEL */
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{ 0x04, 0xf6ff6eff }, /* GP_IO_SEL */
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{ 0x0c, 0x02fe0100 }, /* GP_LVL */
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{ 0x18, 0x00040000 }, /* GPO_BLINK */
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{ 0x1c, 0x00000000 }, /* GP_SER_BLINK */
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{ 0x28, 0x00000000 }, /* GP_NMI_EN + GPI_NMI_STS */
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{ 0x2c, 0x00000000 }, /* GP_INV */
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{ 0x30, 0x020300fe }, /* GPIO_USE_SEL2 */
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{ 0x34, 0x1f57fff4 }, /* GP_IO_SEL2 */
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{ 0x38, 0xa4aa0003 }, /* GP_LVL2 */
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{ 0x40, 0x00000000 }, /* GPIO_USE_SEL3 */
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{ 0x44, 0x00000f00 }, /* GP_IO_SEL3 */
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{ 0x48, 0x00000000 }, /* GP_LVL3 */
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{ 0x60, 0x01000000 }, /* GP_RST_SEL1 */
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{ 0x64, 0x00000000 }, /* GP_RST_SEL2 */
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{ 0x68, 0x00000000 }, /* GP_RST_SEL3 */
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};
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/* Default values for Cougar Point desktop chipsets */
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static const gpio_default_t cp_pch_desktop_defaults[] = {
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{ 0x00, 0xb96ba1ff },
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@ -406,6 +444,35 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
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printf("\n============= GPIOS =============\n\n");
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switch (sb->device_id) {
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case PCI_DEVICE_ID_INTEL_3400:
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case PCI_DEVICE_ID_INTEL_3420:
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case PCI_DEVICE_ID_INTEL_3450:
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case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
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case PCI_DEVICE_ID_INTEL_B55_A:
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case PCI_DEVICE_ID_INTEL_B55_B:
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case PCI_DEVICE_ID_INTEL_H55:
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case PCI_DEVICE_ID_INTEL_H57:
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case PCI_DEVICE_ID_INTEL_P55:
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case PCI_DEVICE_ID_INTEL_Q57:
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gpiobase = pci_read_word(sb, 0x48) & 0xff80;
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gpio_registers = pch_gpio_registers;
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size = ARRAY_SIZE(pch_gpio_registers);
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gpio_defaults = ip_pch_desktop_defaults;
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defaults_size = ARRAY_SIZE(ip_pch_desktop_defaults);
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break;
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case PCI_DEVICE_ID_INTEL_3400_MOBILE:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
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case PCI_DEVICE_ID_INTEL_HM55:
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case PCI_DEVICE_ID_INTEL_HM57:
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case PCI_DEVICE_ID_INTEL_PM55:
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case PCI_DEVICE_ID_INTEL_QM57:
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case PCI_DEVICE_ID_INTEL_QS57:
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gpiobase = pci_read_word(sb, 0x48) & 0xff80;
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gpio_registers = pch_gpio_registers;
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size = ARRAY_SIZE(pch_gpio_registers);
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gpio_defaults = ip_pch_mobile_defaults;
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defaults_size = ARRAY_SIZE(ip_pch_mobile_defaults);
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break;
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case PCI_DEVICE_ID_INTEL_Z68:
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case PCI_DEVICE_ID_INTEL_P67:
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case PCI_DEVICE_ID_INTEL_H67:
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@ -522,29 +589,6 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
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gpio_registers = i631x_gpio_registers;
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size = ARRAY_SIZE(i631x_gpio_registers);
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break;
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case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE:
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case PCI_DEVICE_ID_INTEL_P55:
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case PCI_DEVICE_ID_INTEL_PM55:
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case PCI_DEVICE_ID_INTEL_H55:
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case PCI_DEVICE_ID_INTEL_QM57:
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case PCI_DEVICE_ID_INTEL_H57:
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case PCI_DEVICE_ID_INTEL_HM55:
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case PCI_DEVICE_ID_INTEL_Q57:
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case PCI_DEVICE_ID_INTEL_HM57:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
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case PCI_DEVICE_ID_INTEL_B55_A:
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case PCI_DEVICE_ID_INTEL_QS57:
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case PCI_DEVICE_ID_INTEL_3400:
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case PCI_DEVICE_ID_INTEL_3420:
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case PCI_DEVICE_ID_INTEL_3450:
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case PCI_DEVICE_ID_INTEL_B55_B:
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gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
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gpio_registers = i631x_gpio_registers;
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size = ARRAY_SIZE(i631x_gpio_registers);
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break;
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case PCI_DEVICE_ID_INTEL_82371XX:
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printf("This southbridge has GPIOs in the PM unit.\n");
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return 1;
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@ -656,6 +656,23 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
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printf("\n============= PMBASE ============\n\n");
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switch (sb->device_id) {
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case PCI_DEVICE_ID_INTEL_3400:
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case PCI_DEVICE_ID_INTEL_3420:
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case PCI_DEVICE_ID_INTEL_3450:
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case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
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case PCI_DEVICE_ID_INTEL_B55_A:
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case PCI_DEVICE_ID_INTEL_B55_B:
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case PCI_DEVICE_ID_INTEL_H55:
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case PCI_DEVICE_ID_INTEL_H57:
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case PCI_DEVICE_ID_INTEL_HM55:
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case PCI_DEVICE_ID_INTEL_HM57:
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case PCI_DEVICE_ID_INTEL_P55:
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case PCI_DEVICE_ID_INTEL_PM55:
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case PCI_DEVICE_ID_INTEL_Q57:
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case PCI_DEVICE_ID_INTEL_QM57:
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case PCI_DEVICE_ID_INTEL_QS57:
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case PCI_DEVICE_ID_INTEL_Z68:
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case PCI_DEVICE_ID_INTEL_P67:
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case PCI_DEVICE_ID_INTEL_UM67:
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@ -761,28 +778,6 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
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size = ARRAY_SIZE(i63xx_pm_registers);
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break;
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case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE:
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case PCI_DEVICE_ID_INTEL_P55:
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case PCI_DEVICE_ID_INTEL_PM55:
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case PCI_DEVICE_ID_INTEL_H55:
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case PCI_DEVICE_ID_INTEL_QM57:
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case PCI_DEVICE_ID_INTEL_H57:
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case PCI_DEVICE_ID_INTEL_HM55:
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case PCI_DEVICE_ID_INTEL_Q57:
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case PCI_DEVICE_ID_INTEL_HM57:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
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case PCI_DEVICE_ID_INTEL_B55_A:
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case PCI_DEVICE_ID_INTEL_QS57:
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case PCI_DEVICE_ID_INTEL_3400:
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case PCI_DEVICE_ID_INTEL_3420:
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case PCI_DEVICE_ID_INTEL_3450:
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case PCI_DEVICE_ID_INTEL_B55_B:
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pmbase = pci_read_word(sb, 0x40) & 0xfffc;
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pm_registers = i63xx_pm_registers;
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size = ARRAY_SIZE(i63xx_pm_registers);
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break;
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case 0x1234: // Dummy for non-existent functionality
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printf("This southbridge does not have PMBASE.\n");
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return 1;
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@ -47,23 +47,23 @@ int print_rcba(struct pci_dev *sb)
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case PCI_DEVICE_ID_INTEL_ICH10R:
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case PCI_DEVICE_ID_INTEL_NM10:
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case PCI_DEVICE_ID_INTEL_I63XX:
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case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE:
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case PCI_DEVICE_ID_INTEL_P55:
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case PCI_DEVICE_ID_INTEL_PM55:
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case PCI_DEVICE_ID_INTEL_H55:
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case PCI_DEVICE_ID_INTEL_QM57:
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case PCI_DEVICE_ID_INTEL_H57:
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case PCI_DEVICE_ID_INTEL_HM55:
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case PCI_DEVICE_ID_INTEL_Q57:
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case PCI_DEVICE_ID_INTEL_HM57:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
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case PCI_DEVICE_ID_INTEL_B55_A:
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case PCI_DEVICE_ID_INTEL_QS57:
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case PCI_DEVICE_ID_INTEL_3400:
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case PCI_DEVICE_ID_INTEL_3420:
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case PCI_DEVICE_ID_INTEL_3450:
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case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
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case PCI_DEVICE_ID_INTEL_B55_A:
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case PCI_DEVICE_ID_INTEL_B55_B:
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case PCI_DEVICE_ID_INTEL_H55:
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case PCI_DEVICE_ID_INTEL_H57:
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case PCI_DEVICE_ID_INTEL_HM55:
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case PCI_DEVICE_ID_INTEL_HM57:
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case PCI_DEVICE_ID_INTEL_P55:
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case PCI_DEVICE_ID_INTEL_PM55:
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case PCI_DEVICE_ID_INTEL_Q57:
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case PCI_DEVICE_ID_INTEL_QM57:
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case PCI_DEVICE_ID_INTEL_QS57:
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case PCI_DEVICE_ID_INTEL_Z68:
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case PCI_DEVICE_ID_INTEL_P67:
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case PCI_DEVICE_ID_INTEL_UM67:
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