From b761903b8bbcf33b1f159b7899e0970f2eac6498 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 30 Apr 2021 16:11:37 +0200 Subject: [PATCH] sb/intel/lynxpoint: Fix VBOOT with !CONFIG_INTEL_LYNXPOINT_LP The Intel Basking Ridge CRB does not have a Lynxpoint LP PCH but was using the lp gpio code instead of the southbridge/intel/common code in verstage. Change-Id: I775d3dc3540fbd8a939701d873183dd016e24ba4 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/52790 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons --- src/southbridge/intel/common/Makefile.inc | 1 + src/southbridge/intel/lynxpoint/Makefile.inc | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index adacc25a4b..1fc3a63066 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -27,6 +27,7 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c +verstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index f980a6554d..9ffd764764 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -41,10 +41,10 @@ ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) romstage-y += lp_gpio.c ramstage-y += lp_gpio.c smm-y += lp_gpio.c +verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += lp_gpio.c endif verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += pmutil.c -verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += lp_gpio.c CPPFLAGS_common += -I$(src)/southbridge/intel/lynxpoint/include