mb/google/volteer/halvor: initialize gpio setting and update overridetree.cb
Based on schematic and gpio table of halvor, generate gpio setting and overridetree.cb for halvor. BUG=b:153680359 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Verify that the image-halvor.bin is generated successfully. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ic6bd018551be58945742d1a6e7f7c5560f218e40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Frank Wu
Tim Wawrzynczak
parent
7c34865c92
commit
b763a4febc
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@ -1,15 +1,152 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/gpio.h>
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#include <variant/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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/* Pad configuration in ramstage */
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/* Leave eSPI pins untouched from default settings */
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static const struct pad_config gpio_table[] = {
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/* A0 thru A6 come configured out of reset, do not touch */
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/* A0 : ESPI_IO0 ==> ESPI_IO_0 */
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/* A1 : ESPI_IO1 ==> ESPI_IO_1 */
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/* A2 : ESPI_IO2 ==> ESPI_IO_2 */
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/* A3 : ESPI_IO3 ==> ESPI_IO_3 */
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/* A4 : ESPI_CS# ==> ESPI_CS_L */
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/* A5 : ESPI_CLK ==> ESPI_CLK */
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/* A6 : ESPI_RESET# ==> NC(TP764) */
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/* A7 : I2S2_SCLK ==> I2S1_SCLK */
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PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
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/* A8 : I2S2_SFRM ==> I2S1_SFRM */
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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/* A9 : I2S2_TXD ==> I2S1_TXD */
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PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
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/* A10 : I2S2_RXD ==> I2S1_RXD */
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PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
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/* A18 : DDSP_HPDB ==> NC */
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PAD_NC(GPP_A18, NONE),
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/* A22 : DDPC_CTRLDATA ==> NC */
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PAD_NC(GPP_A22, NONE),
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/* A23 : I2S1_SCLK ==> HP_INT_L */
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PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, EDGE_BOTH),
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/* B2 : VRALERT# ==> NC */
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PAD_NC(GPP_B2, NONE),
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/* B3 : CPU_GP2 ==> NC */
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PAD_NC(GPP_B3, NONE),
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/* B5 : ISH_I2C0_CVF_SDA ==> NC */
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PAD_NC(GPP_B5, NONE),
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/* B6 : ISH_I2C0_CVF_SCL ==> NC */
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PAD_NC(GPP_B6, NONE),
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/* B7 : ISH_12C1_SDA ==> I2C_SENSOR_SDA */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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/* B8 : ISH_I2C1_SCL ==> I2C_SENSOR_SCL */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
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/* C1 : SMBDATA ==> FPMCU_BOOT1 */
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PAD_CFG_GPO(GPP_C1, 0, DEEP),
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/* C7 : SML1DATA ==> NC */
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PAD_NC(GPP_C7, NONE),
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/* C10 : UART0_RTS# ==> USI_RST_L */
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PAD_CFG_GPO(GPP_C10, 1, DEEP),
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/* C11 : UART0_CTS# ==> NC */
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PAD_NC(GPP_C11, NONE),
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/* C13 : UART1_TXD ==> NC */
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PAD_NC(GPP_C13, NONE),
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/* D7 : SRCCLKREQ2# ==> NC */
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PAD_NC(GPP_D7, NONE),
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/* D9 : ISH_SPI_CS# ==> TBT_LSX2_TXD */
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PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4),
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/* D10 : ISH_SPI_CLK ==> TBT_LSX2_RXD */
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PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4),
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/* D11 : ISH_SPI_MISO ==> NC */
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PAD_NC(GPP_D11, NONE),
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/* D12 : ISH_SPI_MOSI ==> NC */
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PAD_NC(GPP_D12, NONE),
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/* E0 : SATAXPCIE0 ==> NC */
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PAD_NC(GPP_E0, NONE),
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/* E1 : SPI1_IO2 ==> NC */
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PAD_NC(GPP_E1, NONE),
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/* E2 : SPI1_IO3 ==> NC */
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PAD_NC(GPP_E2, NONE),
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/* E5 : SATA_DEVSLP1 ==> NC */
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PAD_NC(GPP_E5, NONE),
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/* E10 : SPI1_CS# ==> NC */
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PAD_NC(GPP_E10, NONE),
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/* E12 : SPI1_MISO_IO1 ==> NC */
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PAD_NC(GPP_E12, NONE),
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/* E13 : SPI1_MOSI_IO0 ==> NC */
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PAD_NC(GPP_E13, NONE),
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/* E16 : ISH_GP7 ==> SD_PRSNT# */
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PAD_CFG_GPI(GPP_E16, NONE, DEEP),
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/* E17 : THC0_SPI1_INT# ==> NC */
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PAD_NC(GPP_E17, NONE),
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/* E22 : DDPA_CTRLCLK ==> NC */
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PAD_NC(GPP_E22, NONE),
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/* E23 : DDPA_CTRLDATA ==> NC */
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PAD_NC(GPP_E23, NONE),
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/* F8 : I2S_MCLK2_INOUT ==> NC */
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PAD_NC(GPP_F8, NONE),
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/* F10 : GPPF10_STRAP */
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PAD_NC(GPP_F10, NONE),
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/* F11 : THC1_SPI2_CLK ==> NC */
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PAD_NC(GPP_F11, NONE),
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/* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */
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PAD_CFG_GPO(GPP_F12, 1, DEEP),
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/* F14 : GSXDIN ==> NC */
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PAD_NC(GPP_F14, NONE),
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/* F15 : GSXSRESET# ==> NC */
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PAD_NC(GPP_F15, NONE),
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/* F16 : GSXCLK ==> EN_PP3300_TOUCHSCREEN */
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PAD_CFG_GPO(GPP_F16, 1, DEEP),
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/* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_F17, NONE, DEEP),
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/* F18 : THC1_SPI2_INT# ==> EN_SPKR_PA */
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PAD_CFG_GPO(GPP_F18, 1, DEEP),
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/* F19 : SRCCLKREQ6# ==> NC */
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PAD_NC(GPP_F19, NONE),
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/* H6 : I2C3_SDA */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* H7 : I2C3_SCL */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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/* H12 : M2_SKT2_CFG0 ==> NC */
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PAD_NC(GPP_H12, NONE),
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/* H13 : M2_SKT2_CFG1 # ==> SPKR_INT# */
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PAD_CFG_GPI(GPP_H13, NONE, DEEP),
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/* H14 : M2_SKT2_CFG2 # ==> NC */
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PAD_NC(GPP_H14, NONE),
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/* H15 : M2_SKT2_CFG3 # ==> NC */
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PAD_NC(GPP_H15, NONE),
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/* H16 : DDPB_CTRLCLK ==> NC */
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PAD_NC(GPP_H16, NONE),
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/* H17 : DDPB_CTRLDATA ==> NC */
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PAD_NC(GPP_H17, NONE),
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/* H23 : IMGCLKOUT4 ==> NC */
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PAD_NC(GPP_H23, NONE),
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/* R4 : HDA_RST# ==> NC */
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PAD_NC(GPP_R4, NONE),
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/* R5 : HDA_SDI1 ==> NC */
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PAD_NC(GPP_R5, NONE),
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/* R6 : I2S1_TXD ==> NC */
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PAD_NC(GPP_R6, NONE),
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/* R7 : I2S1_SFRM ==> NC */
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PAD_NC(GPP_R7, NONE),
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/* S4 : SNDW2_CLK ==> SOC_DMIC_CLK1 */
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PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
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/* S5 : SNDW2_DATA ==> SOC_DMIC_DATA1 */
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PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
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/* GPD11: LANPHYC ==> NC */
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PAD_NC(GPD11, NONE),
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};
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const struct pad_config *variant_base_gpio_table(size_t *num)
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const struct pad_config *variant_override_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(gpio_table);
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return gpio_table;
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@ -17,7 +154,38 @@ const struct pad_config *variant_base_gpio_table(size_t *num)
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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/* B11 : PMCALERT# ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
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/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C0 : SMBCLK ==> EN_PP3300_WLAN */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
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/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
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PAD_CFG_GPO(GPP_C22, 0, DEEP),
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/* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
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PAD_CFG_GPO(GPP_H11, 1, DEEP),
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};
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const struct pad_config *variant_early_gpio_table(size_t *num)
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@ -25,12 +193,3 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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static const struct cros_gpio cros_gpios[] = {
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};
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const struct cros_gpio *variant_cros_gpios(size_t *num)
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{
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*num = ARRAY_SIZE(cros_gpios);
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return cros_gpios;
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}
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@ -5,6 +5,8 @@
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#include <baseboard/gpio.h>
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/* Copied from baseboard and may need to change for the new variant. */
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#undef GPIO_EC_IN_RW
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/* EC in RW */
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#define GPIO_EC_IN_RW GPP_F17
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#endif
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@ -1,4 +1,58 @@
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chip soc/intel/tigerlake
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register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0
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register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
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register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera
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register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC2)" # Type-A / Type-C Port 2
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register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
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register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
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register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
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register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A / Type-C Port 2
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register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
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device domain 0 on
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device pci 15.0 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "name" = ""RT58""
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register "desc" = ""Headset Codec""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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chip drivers/i2c/max98373
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register "vmon_slot_no" = "0"
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register "imon_slot_no" = "1"
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register "uid" = "0"
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register "desc" = ""Right Speaker Amp""
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register "name" = ""MAXR""
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device i2c 31 on end
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end
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chip drivers/i2c/max98373
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register "vmon_slot_no" = "2"
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register "imon_slot_no" = "3"
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register "uid" = "1"
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register "desc" = ""Left Speaker Amp""
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register "name" = ""MAXL""
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device i2c 32 on end
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end
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end # I2C #0 0xA0E8
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device pci 1f.3 on
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chip drivers/generic/max98357a
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register "hid" = ""MX98357A""
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register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F18)"
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register "sdmode_delay" = "5"
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device generic 0 on end
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end
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end # Intel HD audio 0xA0C8-A0CF
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end
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end
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