soc/amd/picasso: Add APOB NV back for non-S3
New information indicates the PSP expects the APOB NV region populated for all types of boot, and this is not a feature only used for S3. Switch over to using the MRC_CACHE flash region. Remove the Kconfig symbols for the APOB_NV base and size. Override the MRC_CACHE_SETTINGS_CACHE_SIZE to ensure the default maintains the minimum required size. Use the generated (or mainboard-specified) fmap.fmd file as an input for amdfwtool and properly match the flash region. Change the original naming for the APOB destination, which matched the PSP spec's field name, to PSP_APOB_DESTINATION. This should be more intuitive for a source code reader. The APOB address is the location in DRAM where the PSP puts its output block. BUG=b:147042464, b:153675914 TEST=Boot trembyle Original-Change-Id: Ia5ba8646deec2bd282df930f471738723063eef8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2080375 Original-Change-Id: I972d66f1817f86ff0b689f011c0c44c3fe7c8ef7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2053312 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I4550766ece462b65a6bfe6f1b747343e08e53fe5 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Marshall Dawson
Felix Held
parent
368873ced3
commit
b768723c72
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@ -51,6 +51,7 @@ config CPU_SPECIFIC_OPTIONS
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select PLATFORM_USES_FSP2_0
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select FSP_USES_CB_STACK
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select UDK_2017_BINDING
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select CACHE_MRC_SETTINGS
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select HAVE_CF9_RESET
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config PRERAM_CBMEM_CONSOLE_SIZE
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@ -289,24 +290,23 @@ config AMD_PUBKEY_FILE
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string
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default "3rdparty/amd_blobs/picasso/PSP/AmdPubKeyRV.bin"
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config PSP_APOB_DESTINATION
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config PSP_APOB_DRAM_ADDRESS
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hex
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default 0x9f00000
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help
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Location in DRAM where the PSP will copy the AGESA PSP Output
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Block.
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config PSP_APOB_NV_ADDRESS
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hex "Base address of APOB NV"
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# This value is currently the same as the default defined in
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# drivers/mrc_cache/Kconfig. We do this in in case the default
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# changes. The PSP requires this value to be 64KiB.
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config MRC_SETTINGS_CACHE_SIZE
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hex
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default 0x10000
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help
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Location in flash where the PSP can find the S3 restore information.
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Place this on a boundary that the flash device can erase.
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config PSP_APOB_NV_SIZE
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hex "Size of APOB NV to be reserved"
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help
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Size of the S3 restore information. Make this a multiple of the
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size the flash device can erase.
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Size of flash area used to save APOB NV data which occupies the
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RW_MRC_CACHE region. Make this granularity the flash device can
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erase.
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config USE_PSPSCUREOS
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bool
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@ -181,7 +181,7 @@ endif
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PSP_APCB_FILES=$(foreach f, $(APCB_SOURCES), $(obj)/APCB_$(f).bin)
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# type = 0x61
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PSP_APOB_BASE=$(CONFIG_PSP_APOB_DESTINATION)
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PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
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# type = 0x62
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PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
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@ -192,11 +192,18 @@ PSP_BIOSBIN_SIZE=$(CONFIG_C_ENV_BOOTBLOCK_SIZE)
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# This address must match the BOOTBLOCK logic in arch/x86/memlayout.ld.
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PSP_BIOSBIN_DEST=$(shell printf "%x" $(call int-subtract, $(call int-add, $(CONFIG_X86_RESET_VECTOR) 0x10) $(PSP_BIOSBIN_SIZE)))
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# type = 0x63
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ifeq ($(CONFIG_HAVE_ACPI_RESUME),y)
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PSP_APOBNV_BASE=$(CONFIG_PSP_APOB_NV_ADDRESS)
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PSP_APOBNV_SIZE=$(CONFIG_PSP_APOB_NV_SIZE)
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endif
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# type = 0x63 - construct APOB NV base/size from flash map
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# TODO(b/157068645): Add ability to fmaptool to extract offsets and sizes
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# This code currently assumes the following FMAP structure. If
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# the UNIFIED_MRC_CACHE region is present, it must have a 0 offset.
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# FLASH@* {
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# BIOS@* {
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# RW_MRC_CACHE@* {
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_FLASH_BASE=$(call int-subtract, 0x100000000 $(CONFIG_ROM_SIZE))
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_GET_FLASH_BASE=grep "FLASH" | sed 's/.*FLASH@//' | sed 's/ .*//'
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_GET_BIOS_REG_BASE=grep "BIOS" | sed 's/.*BIOS@//' | sed 's/ .*//'
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_GET_APOBNV_BASE=grep "RW_MRC_CACHE" | sed 's/.*@//' | sed 's/ .*//'
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_GET_APOBNV_SIZE=grep "RW_MRC_CACHE" | sed 's/.*@//' | sed 's/.* //'
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# type2 = 0x64, 0x65
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PSP_PMUI_FILE1=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Imem.csbin
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@ -264,8 +271,6 @@ OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base)
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OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin)
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OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest)
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OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size)
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OPT_APOBNV_ADDR=$(call add_opt_prefix, $(PSP_APOBNV_BASE), --apob-nv-base)
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OPT_APOBNV_SIZE=$(call add_opt_prefix, $(PSP_APOBNV_SIZE), --apob-nv-size)
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OPT_PSP_PMUI_FILE1=$(call add_opt_prefix, $(PSP_PMUI_FILE1), --subprogram 0 --instance 1 --pmu-inst)
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OPT_PSP_PMUI_FILE2=$(call add_opt_prefix, $(PSP_PMUI_FILE2), --subprogram 0 --instance 4 --pmu-inst)
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OPT_PSP_PMUI_FILE3=$(call add_opt_prefix, $(PSP_PMUI_FILE3), --subprogram 1 --instance 1 --pmu-inst)
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@ -359,7 +364,8 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \
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$(call_strip_quotes, $(PSP_IKEK_FILE)) \
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$(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \
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$$(PSP_APCB_FILES) \
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$(AMDFWTOOL)
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$(AMDFWTOOL) \
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$(obj)/fmap.fmd
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rm -f $@
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@printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n"
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$(AMDFWTOOL) \
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@ -373,8 +379,12 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \
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$(OPT_SMUFW2_SUB1_FILE) \
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$(OPT_PSP_APCB_FILES) \
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$(OPT_APOB_ADDR) \
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$(OPT_APOBNV_ADDR) \
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$(OPT_APOBNV_SIZE) \
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--apob-nv-size $(shell printf "0x%x" \
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$(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_SIZE))) \
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--apob-nv-base $(shell printf "0x%x" $(call int-add, \
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$(shell cat $(obj)/fmap.fmd | $(_GET_FLASH_BASE)) \
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$(shell cat $(obj)/fmap.fmd | $(_GET_BIOS_REG_BASE)) \
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$(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_BASE)))) \
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$(OPT_PSP_BIOSBIN_FILE) \
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$(OPT_PSP_BIOSBIN_DEST) \
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$(OPT_PSP_BIOSBIN_SIZE) \
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