exynos5420: get rid of old exynos5420_config_l2_cache()

We set up L2 cache early in romstage now so the old
function is now redundant.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: Icec93810ddd7feb48286d4b600cb2d58af38b7ef
Reviewed-on: https://gerrit.chromium.org/gerrit/65428
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit bb91f1078ea55a7c8bdc19336cef2ec9a5f4511f)

exynos: stack size: Increase the stack size to 16KB.

The lzma decoding function in the RAM stage allocates nearly 16KB on the stack
which is shared between the bootblock, rom stage, and ram stage. The stack had
been much too small and needed to be expanded.

Old-Change-Id: I1b74fff9b54e506320d58956b779b3a102e66868
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65937
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 243d8a80f68dd257ecc5b4e19614bc7f0f5d398b)

exynos: gpio: add a bigger delay when reading board strappings

Z-state pins were not reading reliably with a 5us delay, so increase
it to 15us.

This is ported from https://gerrit.chromium.org/gerrit/64338

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: Ife6ea2ef5989e1a4c17913278ab972f0fd7f7f35
Reviewed-on: https://gerrit.chromium.org/gerrit/65727
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 76f0f8203f1af3f461745cefcc94e97c422d9084)

exynos5420: enable DMC internal clock gating

lets enable memory controller internal clock gating for ddr3.
with these bits enabled we save some power out of ddr3.

This is ported from https://gerrit.chromium.org/gerrit/#/c/60774

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: I2f9b0d78483b3ea7441f54a715c7c1e42eda3f7f
Reviewed-on: https://gerrit.chromium.org/gerrit/65728
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 022a81c44e655a9f81e974e730c0cecc1f048781)

exynos5420: Correct the 600MHz PMS value

In UM ver0.02, 600MHz clock PMS values differs from what is programed
currently. Though this also results in 600MHz clock, but it is better to
match what UM says. This patch chnage this as per UM

This is ported from https://gerrit.chromium.org/gerrit/#/c/65106/3
(Note: we already used the correct 600MHz value for KPLL)

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: I6786815ab33427a23436e6ee37295f6c37dcd3d5
Reviewed-on: https://gerrit.chromium.org/gerrit/65726
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit ceabf57ca78449fa6e9cfd212bdf4774706de92f)

Squashed five commits pertaining to  exynos.

Change-Id: I3fd894aed15b8cd161c30904a46dac7e07eb8992
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6425
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

src/cpu/samsung/exynos5250/Kconfig

@@ -69,21 +69,21 @@ config STACK_TOP
 
 config STACK_BOTTOM
 	hex
-	default 0x02077000
+	default 0x02074000
 
 config STACK_SIZE
 	hex
-	default 0x1000
+	default 0x4000
 
 # TODO We may probably move this to board-specific implementation files instead
 # of KConfig values.
 config CBFS_CACHE_ADDRESS
 	hex "memory address to put CBFS cache data"
-	default 0x02060000
+	default 0x0205c000
 
 config CBFS_CACHE_SIZE
 	hex "size of CBFS cache data"
-	default 0x000017000
+	default 0x00018000
 
 config SYS_SDRAM_BASE
 	hex

src/cpu/samsung/exynos5420/Kconfig

@@ -46,12 +46,12 @@ config CBFS_ROM_OFFSET
 # 0x0202_4400: variable length bootblock checksum header.
 # 0x0202_4410: bootblock, assume up to 32KB in size
 # 0x0203_0000: romstage, assume up to 128KB in size.
-# 0x0206_0000: cache for CBFS data.
+# 0x0205_c000: cache for CBFS data.
+# 0x0206_f000: stack bottom
+# 0x0207_3000: stack pointer
 # 0x0207_3000: shared (with kernel) page for cpu & secondary core states.
 #              the shared data is currently only <0x50 bytes so we can share
 #              this page with stack.
-# 0x0207_3100: stack bottom
-# 0x0207_4000: stack pointer
 
 config BOOTBLOCK_BASE
 	hex
@@ -63,7 +63,7 @@ config ROMSTAGE_BASE
 
 config ROMSTAGE_SIZE
 	hex
-	default 0x10000
+	default 0x20000
 
 # Stack may reside in either IRAM or DRAM. We will define it to live
 # at the top of IRAM for now.
@@ -72,25 +72,25 @@ config ROMSTAGE_SIZE
 # consecutive memory locations ending just below SP
 config STACK_TOP
 	hex
-	default 0x02074000
+	default 0x02073000
 
 config STACK_BOTTOM
 	hex
-	default 0x02073100
+	default 0x0206f000
 
 config STACK_SIZE
 	hex
-	default 0x0f00
+	default 0x4000
 
 # TODO We may probably move this to board-specific implementation files instead
 # of KConfig values.
 config CBFS_CACHE_ADDRESS
 	hex "memory address to put CBFS cache data"
-	default 0x02060000
+	default 0x0205c000
 
 config CBFS_CACHE_SIZE
 	hex "size of CBFS cache data"
-	default 0x000013000
+	default 0x00013000
 
 config SYS_SDRAM_BASE
 	hex

src/cpu/samsung/exynos5420/clock_init.c

@@ -81,7 +81,7 @@ void system_clock_init(void)
 
 	/* Set KPLL*/
 	writel(KPLL_CON1_VAL, &clk->kpll_con1);
-	val = set_pll(0xc8, 0x2, 0x2);
+	val = set_pll(0x190, 0x4, 0x2);
 	writel(val, &clk->kpll_con0);
 	while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
 		;

src/cpu/samsung/exynos5420/cpu.c

@@ -206,33 +206,3 @@ struct chip_operations cpu_samsung_exynos5420_ops = {
 	CHIP_NAME("CPU Samsung Exynos 5420")
 	.enable_dev = enable_exynos5420_dev,
 };
-
-void exynos5420_config_l2_cache(void)
-{
-	uint32_t val;
-
-	/*
-	 * Bit    9 - L2 tag RAM setup (1 cycle)
-	 * Bits 8:6 - L2 tag RAM latency (3 cycles)
-	 * Bit    5 - L2 data RAM setup (1 cycle)
-	 * Bits 2:0 - L2 data RAM latency (3 cycles)
-	 */
-	val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2);
-	write_l2ctlr(val);
-
-	val = read_l2actlr();
-
-	/* L2ACTLR[3]: Disable clean/evict push to external */
-	val |= (1 << 3);
-
-	/* L2ACTLR[7]: Enable hazard detect timeout for A15 */
-	val |= (1 << 7);
-
-	/* L2ACTLR[27]: Prevents stopping the L2 logic clock */
-	val |= (1 << 27);
-
-	write_l2actlr(val);
-
-	/* Read the l2 control register to force things to take effect? */
-	val = read_l2ctlr();
-}

src/cpu/samsung/exynos5420/cpu.h

@@ -263,7 +263,6 @@ static inline u32 get_fb_base_kb(void)
 }
 
 /* Procedures to setup Exynos5420 CPU */
-void exynos5420_config_l2_cache(void);
 void exynos5420_config_smp(void);
 
 #endif	/* _EXYNOS5420_CPU_H */

src/cpu/samsung/exynos5420/dmc_init_ddr3.c

@@ -376,5 +376,13 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 	writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
 		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
 		&drex1->concontrol);
+
+	/* Enable Clock Gating Control for DMC
+	 * this saves around 25 mw dmc power as compared to the power
+	 * consumption without these bits enabled
+	 */
+	setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
+	setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
+
 	return 0;
 }

src/cpu/samsung/exynos5420/gpio.c

@@ -206,10 +206,10 @@ int gpio_set_value(unsigned gpio, int value)
 
 /*
  * Add a delay here to give the lines time to settle
- * TODO(sjg): 1us does not always work, 2 is stable, so use 5 to be safe
+ * TODO(dianders): 5us does not always work, 10 is stable, so use 15 to be safe
  * Come back to this and sort out what the datasheet says
  */
-#define GPIO_DELAY_US 5
+#define GPIO_DELAY_US	15
 
 #ifndef __BOOT_BLOCK__
 /*

src/cpu/samsung/exynos5420/setup.h

@@ -791,6 +791,14 @@ struct exynos5_phy_control;
 #define BRBRSVCONTROL_VAL	0x00000033
 #define BRBRSVCONFIG_VAL	0x88778877
 
+/* Clock Gating Control (CGCONTROL) register */
+#define MEMIF_CG_EN	(1 << 3) /* Memory interface clock gating */
+#define SCG_CG_EN	(1 << 2) /* Scheduler clock gating */
+#define BUSIF_WR_CG_EN	(1 << 1) /* Bus interface write channel clock gating */
+#define BUSIF_RD_CG_EN	(1 << 0) /* Bus interface read channel clock gating */
+#define DMC_INTERNAL_CG	(MEMIF_CG_EN | SCG_CG_EN | \
+				 BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)
+
 /* DMC PHY Control0 register */
 #define PHY_CONTROL0_RESET_VAL	0x0
 #define MEM_TERM_EN	(1 << 31)	/* Termination enable for memory */

src/cpu/samsung/exynos5420/smp.c

@@ -271,7 +271,10 @@ static void power_down_core(void)
 /* Configures the CPU states shard memory page and then shutdown all cores. */
 static void configure_secondary_cores(void)
 {
-	configure_l2ctlr();
+	if (get_bits(read_midr(), 4, 12) == PART_NUMBER_CORTEX_A15) {
+		configure_l2ctlr();
+		configure_l2actlr();
+	}
 
 	/* Currently we use power_down_core as callback for each core to
 	 * shutdown itself, but it is also ok to directly set ARM_CORE*_CONFIG

src/mainboard/google/pit/mainboard.c

@@ -434,7 +434,6 @@ static void mainboard_enable(device_t dev)
 
 	/* set up dcache and MMU */
 	/* FIXME: this should happen via resource allocator */
-	exynos5420_config_l2_cache();
 	mmu_init();
 	mmu_config_range(0, DRAM_START, DCACHE_OFF);
 	mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);