arm64: psci: add node hierarchy
In order to properly support more arm64 SoCs PSCI needs to handle the hierarchy of cpus/clusters within the SoC. The nodes within PSCI are kept in a tree as well as a depth-first ordered array of same tree. Additionally, the PSCI states are now maintained in a hierachal manner. OFF propogates up the tree as long as all siblings are set to OFF. ON propogates up the tree until a node is not already set to OFF. The SoC provides the operations for determining how many children are at a given affinity level. Lastly, the secmon startup has been reworked in that all non-BSP CPUs wait for instructions from the BSP. BUG=chrome-os-partner:32136 BRANCH=None TEST=Can still boot into kernel with SMP. Change-Id: I036fabaf0f1cefa2841264c47e4092c75a2ff4dc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 721d408cd110e1b56d38789177b740aa0e54ca33 Original-Change-Id: I520a9726e283bee7edcb514cda28ec1eb31b5ea0 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226480 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9390 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin
Patrick Georgi
parent
7d62ad05fb
commit
b777f3e3d1
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@ -28,23 +28,14 @@
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#include <console/console.h>
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#include "secmon.h"
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enum {
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PSCI_CPU_STATE_OFF = 0,
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PSCI_CPU_STATE_ON_PENDING,
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PSCI_CPU_STATE_ON,
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};
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struct psci_cpu_state {
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uint64_t mpidr;
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void *entry;
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void *arg;
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int state;
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};
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DECLARE_SPIN_LOCK(psci_spinlock);
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static struct psci_cpu_state psci_state[CONFIG_MAX_CPUS];
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/* Root of PSCI node tree. */
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static struct psci_node psci_root;
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/* Array of all the psci_nodes in system. */
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static size_t psci_num_nodes;
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static struct psci_node **psci_nodes;
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static inline void psci_lock(void)
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{
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@ -56,33 +47,173 @@ static inline void psci_unlock(void)
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spin_unlock(&psci_spinlock);
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}
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static inline int psci_cpu_state_locked(int i)
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static inline int psci_state_locked(const struct psci_node *e)
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{
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return psci_state[i].state;
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return e->state;
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}
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static inline void psci_cpu_set_state_locked(int i, int s)
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static inline void psci_set_state_locked(struct psci_node *e, int s)
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{
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psci_state[i].state = s;
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e->state = s;
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}
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static struct cpu_info *mpidr_to_cpu_info(uint64_t mpidr)
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static struct psci_node *psci_node_lookup(uint64_t mpidr, int level)
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{
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int i;
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size_t i;
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for (i = 0; i < ARRAY_SIZE(psci_state); i++) {
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if (mpidr == psci_state[i].mpidr)
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return cpu_info_for_cpu(i);
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/* The array of node pointers are in depth-first order of the tree. */
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for (i = 0; i < psci_num_nodes; i++) {
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struct psci_node *current = psci_nodes[i];
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if (current->mpidr > mpidr)
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break;
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if (current->mpidr < mpidr)
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continue;
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if (current->level == level)
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return current;
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}
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return NULL;
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}
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static inline struct psci_node *node_self(void)
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{
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return psci_node_lookup(cpu_info()->mpidr, PSCI_AFFINITY_LEVEL_0);
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}
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/* Find the ancestor of node affected by a state transition limited by level. */
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static struct psci_node *psci_find_ancestor(struct psci_node *e, int level,
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int state)
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{
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struct psci_node *p;
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/* If all siblings of the node are already off then parent can be
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* set to off as well. */
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if (state == PSCI_STATE_OFF) {
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while (1) {
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size_t i;
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struct psci_node *s;
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if (psci_root_node(e))
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return e;
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p = psci_node_parent(e);
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if (p->level > level)
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return e;
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for (i = 0; i < p->children.num; i++) {
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s = &p->children.nodes[i];
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/* Don't check target. */
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if (s == e)
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continue;
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if (psci_state_locked(s) != PSCI_STATE_OFF)
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return e;
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}
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e = p;
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}
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}
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/* All ancestors in state OFF are affected. */
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if (state == PSCI_STATE_ON_PENDING) {
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while (1) {
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/* At the root. Return last affected node. */
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if (psci_root_node(e))
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return e;
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p = psci_node_parent(e);
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if (p->level > level)
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return e;
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/* This parent is already ON. */
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if (psci_state_locked(p) != PSCI_STATE_OFF)
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return e;
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e = p;
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}
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}
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/* Default to returning node passed in. */
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return e;
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}
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static void psci_set_hierarchy_state(struct psci_node *from,
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struct psci_node *to,
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int state)
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{
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struct psci_node *end;
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end = psci_node_parent(to);
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while (from != end) {
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/* Raced with another CPU as state is already set. */
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if (psci_state_locked(from) == state)
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break;
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psci_set_state_locked(from, state);
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from = psci_node_parent(from);
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}
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}
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static void psci_cpu_on_callback(void *arg)
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{
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struct psci_cpu_state *s = arg;
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struct exc_state state;
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int target_el;
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struct psci_node *e = arg;
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psci_turn_on_self(s->entry, s->arg);
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psci_lock();
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psci_set_hierarchy_state(e, e->cpu_state.ancestor, PSCI_STATE_ON);
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psci_unlock();
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/* Target EL is determined if HVC is enabled or not. */
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target_el = (raw_read_scr_el3() & SCR_HVC_ENABLE) ? EL2 : EL1;
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memset(&state, 0, sizeof(state));
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state.elx.spsr = get_eret_el(target_el, SPSR_USE_H);
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transition_with_entry(e->cpu_state.entry, e->cpu_state.arg, &state);
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}
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static void psci_cpu_on_prepare(struct psci_node *e,
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void *entry, void *arg)
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{
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struct psci_node *ancestor;
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int state = PSCI_STATE_ON_PENDING;
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e->cpu_state.entry = entry;
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e->cpu_state.arg = arg;
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ancestor = psci_find_ancestor(e, PSCI_AFFINITY_LEVEL_HIGHEST, state);
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e->cpu_state.ancestor = ancestor;
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psci_set_hierarchy_state(e, ancestor, state);
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}
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static int psci_schedule_cpu_on(struct psci_node *e)
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{
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struct cpu_action action = {
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.run = &psci_cpu_on_callback,
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.arg = e,
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};
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if (arch_run_on_cpu_async(e->cpu_state.ci->id, &action))
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return PSCI_RET_INTERNAL_FAILURE;
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return PSCI_RET_SUCCESS;
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}
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void psci_turn_on_self(void *entry, void *arg)
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{
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struct psci_node *e = node_self();
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if (e == NULL) {
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printk(BIOS_ERR, "Couldn't turn on self: mpidr %llx\n",
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cpu_info()->mpidr);
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return;
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}
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psci_lock();
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psci_cpu_on_prepare(e, entry, arg);
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psci_unlock();
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psci_schedule_cpu_on(e);
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}
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static void psci_cpu_on(struct psci_func *pf)
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@ -90,60 +221,68 @@ static void psci_cpu_on(struct psci_func *pf)
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uint64_t entry;
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uint64_t target_mpidr;
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uint64_t context_id;
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struct cpu_info *ci;
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int cpu_state;
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struct cpu_action action;
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struct psci_node *e;
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target_mpidr = psci64_arg(pf, PSCI_PARAM_0);
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entry = psci64_arg(pf, PSCI_PARAM_1);
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context_id = psci64_arg(pf, PSCI_PARAM_2);
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ci = mpidr_to_cpu_info(target_mpidr);
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e = psci_node_lookup(target_mpidr, PSCI_AFFINITY_LEVEL_0);
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if (ci == NULL) {
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if (e == NULL) {
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psci32_return(pf, PSCI_RET_INVALID_PARAMETERS);
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return;
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}
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psci_lock();
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cpu_state = psci_cpu_state_locked(ci->id);
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cpu_state = psci_state_locked(e);
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if (cpu_state == PSCI_CPU_STATE_ON_PENDING) {
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if (cpu_state == PSCI_STATE_ON_PENDING) {
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psci32_return(pf, PSCI_RET_ON_PENDING);
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psci_unlock();
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return;
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} else if (cpu_state == PSCI_CPU_STATE_ON) {
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} else if (cpu_state == PSCI_STATE_ON) {
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psci32_return(pf, PSCI_RET_ALREADY_ON);
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psci_unlock();
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return;
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}
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psci_cpu_set_state_locked(ci->id, PSCI_CPU_STATE_ON_PENDING);
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/* Set the parameters and initialize the action. */
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psci_state[ci->id].entry = (void *)(uintptr_t)entry;
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psci_state[ci->id].arg = (void *)(uintptr_t)context_id;
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action.run = &psci_cpu_on_callback;
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action.arg = &psci_state[ci->id];
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if (arch_run_on_cpu_async(ci->id, &action)) {
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psci32_return(pf, PSCI_RET_INTERNAL_FAILURE);
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psci_unlock();
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return;
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}
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psci_cpu_on_prepare(e, (void *)entry, (void *)context_id);
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psci_unlock();
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psci32_return(pf, PSCI_RET_SUCCESS);
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psci32_return(pf, psci_schedule_cpu_on(e));
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}
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static void psci_cpu_off(struct psci_func *pf)
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static int psci_turn_off_node(struct psci_node *e, int level,
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int state_id)
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{
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struct psci_node *ancestor;
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psci_lock();
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psci_cpu_set_state_locked(cpu_info()->id, PSCI_CPU_STATE_OFF);
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ancestor = psci_find_ancestor(e, level, PSCI_STATE_OFF);
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psci_set_hierarchy_state(e, ancestor, PSCI_STATE_OFF);
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psci_unlock();
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/* TODO(adurbin): writeback cache and actually turn off CPU. */
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secmon_trampoline(&secmon_wait_for_action, NULL);
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return PSCI_RET_SUCCESS;
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}
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int psci_turn_off_self(void)
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{
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struct psci_node *e = node_self();
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if (e == NULL) {
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printk(BIOS_ERR, "No PSCI node for MPIDR %llx.\n",
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cpu_info()->mpidr);
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return PSCI_RET_INTERNAL_FAILURE;
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}
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/* -1 state id indicates to SoC to make its own decision for
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* internal state when powering off the node. */
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return psci_turn_off_node(e, PSCI_AFFINITY_LEVEL_HIGHEST, -1);
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}
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static int psci_handler(struct smc_call *smc)
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@ -158,7 +297,7 @@ static int psci_handler(struct smc_call *smc)
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psci_cpu_on(pf);
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break;
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case PSCI_CPU_OFF64:
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psci_cpu_off(pf);
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psci32_return(pf, psci_turn_off_self());
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break;
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default:
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psci32_return(pf, PSCI_RET_NOT_SUPPORTED);
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@ -168,41 +307,190 @@ static int psci_handler(struct smc_call *smc)
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return 0;
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}
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static void psci_link_cpu_info(void *arg)
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{
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struct psci_node *e = node_self();
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if (e == NULL) {
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printk(BIOS_ERR, "No PSCI node for MPIDR %llx.\n",
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cpu_info()->mpidr);
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return;
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}
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e->cpu_state.ci = cpu_info();
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}
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static int psci_init_node(struct psci_node *e,
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struct psci_node *parent,
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int level, uint64_t mpidr)
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{
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size_t i;
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uint64_t mpidr_inc;
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struct psci_node_group *ng;
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size_t num_children;
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memset(e, 0, sizeof(*e));
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e->mpidr = mpidr;
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psci_set_state_locked(e, PSCI_STATE_OFF);
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e->parent = parent;
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e->level = level;
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if (level == PSCI_AFFINITY_LEVEL_0)
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return 0;
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num_children = soc_psci_ops.children_at_level(level, mpidr);
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if (num_children == 0)
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return 0;
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ng = &e->children;
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ng->num = num_children;
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ng->nodes = malloc(ng->num * sizeof(struct psci_node));
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if (ng->nodes == NULL) {
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printk(BIOS_DEBUG, "PSCI: Allocation failure at level %d\n",
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level);
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return -1;
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}
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/* Switch to next level below. */
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level = psci_level_below(level);
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mpidr_inc = mpidr_mask(!!(level == PSCI_AFFINITY_LEVEL_3),
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!!(level == PSCI_AFFINITY_LEVEL_2),
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!!(level == PSCI_AFFINITY_LEVEL_1),
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!!(level == PSCI_AFFINITY_LEVEL_0));
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for (i = 0; i < ng->num; i++) {
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struct psci_node *c = &ng->nodes[i];
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/* Recursively initialize the nodes. */
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if (psci_init_node(c, e, level, mpidr))
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return -1;
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mpidr += mpidr_inc;
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}
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return 0;
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}
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static size_t psci_count_children(struct psci_node *e)
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{
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size_t i;
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size_t count;
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if (e->level == PSCI_AFFINITY_LEVEL_0)
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return 0;
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count = e->children.num;
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for (i = 0; i < e->children.num; i++)
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count += psci_count_children(&e->children.nodes[i]);
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return count;
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}
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static size_t psci_write_nodes(struct psci_node *e, size_t index)
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{
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size_t i;
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/*
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* Recursively save node pointers in array. Node pointers are
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* ordered in ascending mpidr and descending level within same mpidr.
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* i.e. each node is saved in depth-first order of the tree.
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*/
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if (e->level != PSCI_AFFINITY_ROOT) {
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psci_nodes[index] = e;
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index++;
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}
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if (e->level == PSCI_AFFINITY_LEVEL_0)
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return index;
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for (i = 0; i < e->children.num; i++)
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index = psci_write_nodes(&e->children.nodes[i], index);
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return index;
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}
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static int psci_allocate_nodes(void)
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{
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int level;
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size_t num_children;
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uint64_t mpidr;
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struct psci_node *e;
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mpidr = 0;
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level = PSCI_AFFINITY_ROOT;
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/* Find where the root should start. */
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while (psci_level_below(level) >= PSCI_AFFINITY_LEVEL_0) {
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num_children = soc_psci_ops.children_at_level(level, mpidr);
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if (num_children == 0) {
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printk(BIOS_ERR, "PSCI: No children at level %d!\n",
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level);
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return -1;
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}
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/* The root starts where the affinity levels branch. */
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if (num_children > 1)
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break;
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level = psci_level_below(level);
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}
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if (psci_init_node(&psci_root, NULL, level, mpidr)) {
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printk(BIOS_ERR, "PSCI init node failure.\n");
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return -1;
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}
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num_children = psci_count_children(&psci_root);
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/* Count the root node if isn't a fake node. */
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if (psci_root.level != PSCI_AFFINITY_ROOT)
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num_children++;
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|
||||
psci_nodes = malloc(num_children * sizeof(void *));
|
||||
psci_num_nodes = num_children;
|
||||
|
||||
if (psci_nodes == NULL) {
|
||||
printk(BIOS_ERR, "PSCI node pointer array failure.\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
num_children = psci_write_nodes(&psci_root, 0);
|
||||
if (num_children != psci_num_nodes) {
|
||||
printk(BIOS_ERR, "Wrong nodes written: %zd vs %zd.\n",
|
||||
num_children, psci_num_nodes);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* By default all nodes are set to PSCI_STATE_OFF. In order not
|
||||
* to race with other CPUs turning themselves off set the BSPs
|
||||
* affinity node to ON.
|
||||
*/
|
||||
e = node_self();
|
||||
if (e == NULL) {
|
||||
printk(BIOS_ERR, "No PSCI node for BSP.\n");
|
||||
return -1;
|
||||
}
|
||||
psci_set_state_locked(e, PSCI_STATE_ON);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void psci_init(void)
|
||||
{
|
||||
struct cpu_info *ci;
|
||||
uint64_t mpidr;
|
||||
struct cpu_action action = {
|
||||
.run = &psci_link_cpu_info,
|
||||
};
|
||||
|
||||
/* Set this CPUs MPIDR clearing the bits that are not per-cpu. */
|
||||
ci = cpu_info();
|
||||
mpidr = raw_read_mpidr_el1();
|
||||
mpidr &= ~(1ULL << 31); /* RES1 */
|
||||
mpidr &= ~(1ULL << 30); /* U */
|
||||
mpidr &= ~(1ULL << 24); /* MT */
|
||||
psci_state[ci->id].mpidr = mpidr;
|
||||
|
||||
if (!cpu_is_bsp())
|
||||
if (psci_allocate_nodes()) {
|
||||
printk(BIOS_ERR, "PSCI support not enabled.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (arch_run_on_all_cpus_async(&action))
|
||||
printk(BIOS_ERR, "Error linking cpu_info to PSCI nodes.\n");
|
||||
|
||||
/* Register PSCI handlers. */
|
||||
if (smc_register_range(PSCI_CPU_OFF64, PSCI_CPU_ON64, &psci_handler))
|
||||
printk(BIOS_ERR, "Couldn't register PSCI handler.\n");
|
||||
}
|
||||
|
||||
void psci_turn_on_self(void *entry, void *arg)
|
||||
{
|
||||
struct exc_state state;
|
||||
int target_el;
|
||||
struct cpu_info *ci = cpu_info();
|
||||
|
||||
psci_lock();
|
||||
psci_cpu_set_state_locked(ci->id, PSCI_CPU_STATE_ON);
|
||||
psci_unlock();
|
||||
|
||||
/* Target EL is determined if HVC is enabled or not. */
|
||||
target_el = (raw_read_scr_el3() & SCR_HVC_ENABLE) ? EL2 : EL1;
|
||||
|
||||
memset(&state, 0, sizeof(state));
|
||||
state.elx.spsr = get_eret_el(target_el, SPSR_USE_H);
|
||||
transition_with_entry(entry, arg, &state);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -30,6 +30,18 @@
|
|||
#include <stddef.h>
|
||||
#include "secmon.h"
|
||||
|
||||
/* Save initial secmon params per CPU to handle turn up. */
|
||||
static struct secmon_params *init_params[CONFIG_MAX_CPUS];
|
||||
|
||||
static void start_up_cpu(void *arg)
|
||||
{
|
||||
struct secmon_params *params = init_params[cpu_info()->id];
|
||||
|
||||
if (params == NULL)
|
||||
psci_turn_off_self();
|
||||
psci_turn_on_self(params->entry, params->arg);
|
||||
}
|
||||
|
||||
static void cpu_init(int bsp)
|
||||
{
|
||||
struct cpu_info *ci = cpu_info();
|
||||
|
|
@ -43,17 +55,26 @@ static void cpu_init(int bsp)
|
|||
|
||||
static void secmon_init(struct secmon_params *params, int bsp)
|
||||
{
|
||||
struct cpu_action action = {
|
||||
.run = start_up_cpu,
|
||||
};
|
||||
|
||||
exception_hwinit();
|
||||
cpu_init(bsp);
|
||||
|
||||
init_params[cpu_info()->id] = params;
|
||||
|
||||
if (!cpu_is_bsp())
|
||||
secmon_wait_for_action();
|
||||
|
||||
smc_init();
|
||||
psci_init();
|
||||
|
||||
/* Turn on CPU if params are not NULL. */
|
||||
if (params != NULL)
|
||||
psci_turn_on_self(params->entry, params->arg);
|
||||
arch_run_on_all_cpus_async(&action);
|
||||
|
||||
secmon_wait_for_action();
|
||||
printk(BIOS_ERR, "CPU turn on failed for BSP.\n");
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
void secmon_wait_for_action(void)
|
||||
|
|
|
|||
|
|
@ -140,7 +140,7 @@ static struct exception_handler smc_handler32 = {
|
|||
.handler = &smc_handler,
|
||||
};
|
||||
|
||||
void smc_init(void)
|
||||
static void enable_smc(void *arg)
|
||||
{
|
||||
uint32_t scr;
|
||||
|
||||
|
|
@ -149,9 +149,15 @@ void smc_init(void)
|
|||
scr &= ~(SCR_SMC_MASK);
|
||||
scr |= SCR_SMC_ENABLE;
|
||||
raw_write_scr_el3(scr);
|
||||
}
|
||||
|
||||
if (!cpu_is_bsp())
|
||||
return;
|
||||
void smc_init(void)
|
||||
{
|
||||
struct cpu_action action = {
|
||||
.run = enable_smc,
|
||||
};
|
||||
|
||||
arch_run_on_all_cpus_async(&action);
|
||||
|
||||
/* Register SMC handlers. */
|
||||
exception_handler_register(EXC_VID_LOW64_SYNC, &smc_handler64);
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@
|
|||
#ifndef __ARCH_PSCI_H__
|
||||
#define __ARCH_PSCI_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <arch/smc.h>
|
||||
|
||||
/* Return Values */
|
||||
|
|
@ -35,6 +37,85 @@ enum {
|
|||
PSCI_RET_DISABLED = -8,
|
||||
};
|
||||
|
||||
/* Generic PSCI state. */
|
||||
enum {
|
||||
PSCI_STATE_OFF = 0,
|
||||
PSCI_STATE_ON_PENDING,
|
||||
PSCI_STATE_ON,
|
||||
};
|
||||
|
||||
/* Affinity level support. */
|
||||
enum {
|
||||
PSCI_AFFINITY_LEVEL_0,
|
||||
PSCI_AFFINITY_LEVEL_1,
|
||||
PSCI_AFFINITY_LEVEL_2,
|
||||
PSCI_AFFINITY_LEVEL_3,
|
||||
PSCI_AFFINITY_ROOT,
|
||||
PSCI_AFFINITY_LEVEL_HIGHEST = PSCI_AFFINITY_ROOT,
|
||||
};
|
||||
|
||||
static inline int psci_level_below(int level)
|
||||
{
|
||||
return level - 1;
|
||||
}
|
||||
|
||||
struct psci_node;
|
||||
|
||||
struct psci_cpu_state {
|
||||
struct cpu_info *ci;
|
||||
void *entry;
|
||||
void *arg;
|
||||
/* Ancestor of target to update state in CPU_ON case. */
|
||||
struct psci_node *ancestor;
|
||||
};
|
||||
|
||||
struct psci_node_group {
|
||||
size_t num;
|
||||
struct psci_node *nodes;
|
||||
};
|
||||
|
||||
struct psci_node {
|
||||
uint64_t mpidr;
|
||||
/* Affinity level of node. */
|
||||
int level;
|
||||
/* Generic power state of this entity. */
|
||||
int state;
|
||||
/* The SoC can stash its own state accounting in here. */
|
||||
int soc_state;
|
||||
/* Parent of curernt entity. */
|
||||
struct psci_node *parent;
|
||||
/*
|
||||
* CPUs are leaves in the tree. They don't have children. The
|
||||
* CPU-specific bits of storage can be shared with the children
|
||||
* storage.
|
||||
*/
|
||||
union {
|
||||
struct psci_node_group children;
|
||||
struct psci_cpu_state cpu_state;
|
||||
};
|
||||
};
|
||||
|
||||
static inline struct psci_node *psci_node_parent(const struct psci_node *n)
|
||||
{
|
||||
return n->parent;
|
||||
}
|
||||
|
||||
static inline int psci_root_node(const struct psci_node *n)
|
||||
{
|
||||
return psci_node_parent(n) == NULL;
|
||||
}
|
||||
|
||||
struct psci_soc_ops {
|
||||
/*
|
||||
* Return number of entities one level below given parent affinitly
|
||||
* level and mpidr.
|
||||
*/
|
||||
size_t (*children_at_level)(int parent_level, uint64_t mpidr);
|
||||
};
|
||||
|
||||
/* Each SoC needs to provide the functions in the psci_soc_ops structure. */
|
||||
extern struct psci_soc_ops soc_psci_ops;
|
||||
|
||||
/* PSCI Functions. */
|
||||
enum {
|
||||
/* 32-bit System level functions. */
|
||||
|
|
@ -111,5 +192,6 @@ void psci_init(void);
|
|||
|
||||
/* Turn on the current CPU within the PSCI subsystem. */
|
||||
void psci_turn_on_self(void *entry, void *arg);
|
||||
int psci_turn_off_self(void);
|
||||
|
||||
#endif /* __ARCH_PSCI_H__ */
|
||||
|
|
|
|||
|
|
@ -88,6 +88,7 @@ ramstage-y += ../tegra/usb.c
|
|||
ramstage-$(CONFIG_ARCH_USE_SECURE_MONITOR) += secmon.c
|
||||
|
||||
secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += cpu_lib.S
|
||||
secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += psci.c
|
||||
secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += uart.c
|
||||
|
||||
modules_arm-y += monotonic_timer.c
|
||||
|
|
|
|||
|
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/psci.h>
|
||||
|
||||
static size_t children_at_level(int parent_level, uint64_t mpidr)
|
||||
{
|
||||
if (mpidr != 0)
|
||||
return 0;
|
||||
|
||||
/* T132 just has 2 cores. 0. Level 1 has 2 children at level 0. */
|
||||
switch (parent_level) {
|
||||
case PSCI_AFFINITY_ROOT:
|
||||
return 1;
|
||||
case PSCI_AFFINITY_LEVEL_3:
|
||||
return 1;
|
||||
case PSCI_AFFINITY_LEVEL_2:
|
||||
return 1;
|
||||
case PSCI_AFFINITY_LEVEL_1:
|
||||
return 2;
|
||||
case PSCI_AFFINITY_LEVEL_0:
|
||||
return 0;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
struct psci_soc_ops soc_psci_ops = {
|
||||
.children_at_level = &children_at_level,
|
||||
};
|
||||
Loading…
Reference in New Issue