amd/stoneyridge: Add ACPI MMIO and PCI offsets to ASL
Define various AMD_SB_ACPI_MMIO_ADDR registers at 0xfed80000. Define various PCI config space registers. These are duplicated from AMD's FchCarrizo.asl file. BUG=b:77602074 Change-Id: Ie7447fef682424b05fa912b60c7b80112c6202de Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28768 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marshall Dawson
Martin Roth
parent
1d9a46ba9a
commit
b77c76c271
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@ -185,3 +185,245 @@ Method(OSFL, 0){
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}
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Return(OSVR)
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}
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OperationRegion(SMIC, SystemMemory, 0xfed80000, 0x80000)
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Field( SMIC, ByteAcc, NoLock, Preserve) {
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offset (0x03ee),
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U3PS, 2, /* Usb3PowerSel */
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offset (0x0e28),
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,29 ,
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SARP, 1, /* Sata Ref Clock Powerdown */
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U2RP, 1, /* Usb2 Ref Clock Powerdown */
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U3RP, 1, /* Usb3 Ref Clock Powerdown */
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offset (0x1c00),
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, 1,
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,6,
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U3PY, 1,
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, 7,
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UD3P, 1, /* bit 15 */
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U3PR, 1, /* bit 16 */
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, 11,
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FWLM, 1, /* FirmWare Load Mode */
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FPLS, 1, /* Fw PreLoad Start */
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FPLC, 1, /* Fw PreLoad Complete */
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offset (0x1c04),
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UA04, 16,
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, 15,
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ROAM, 1, /* 1= ROM 0=RAM */
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offset (0x1c08),
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UA08, 32,
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offset (0x1e4a),
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I0TD, 2,
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, 1,
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I0PD, 1,
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offset (0x1e4b),
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I0DS, 3,
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offset (0x1e4c),
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I1TD, 2,
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, 1,
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I1PD, 1,
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offset (0x1e4d),
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I1DS, 3,
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offset (0x1e4e),
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I2TD, 2,
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, 1,
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I2PD, 1,
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offset (0x1e4f),
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I2DS, 3,
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offset (0x1e50),
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I3TD, 2,
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, 1,
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I3PD, 1,
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offset (0x1e51),
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I3DS, 3,
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offset (0x1e56),
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U0TD, 2,
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, 1,
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U0PD, 1,
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offset (0x1e57),
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U0DS, 3,
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offset (0x1e58),
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U1TD, 2,
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, 1,
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U1PD, 1,
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offset (0x1e59),
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U1DS, 3,
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offset (0x1e5e),
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SATD, 2,
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, 1,
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SAPD, 1,
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offset (0x1e5f),
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SADS, 3,
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offset (0x1e64),
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U2TD, 2,
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, 1,
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U2PD, 1,
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offset (0x1e65),
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U2DS, 3,
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offset (0x1e6e),
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U3TD, 2,
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, 1,
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U3PD, 1,
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offset (0x1e6f),
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U3DS, 3,
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offset (0x1e70),
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SDTD, 2,
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, 1,
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, 1,
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, 2,
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SDRT, 1,
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SDSC, 1,
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offset (0x1e71),
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SDDS, 3,
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offset (0x1e80),
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, 15,
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RQ15, 1,
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, 2,
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RQ18, 1,
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, 4,
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RQ23, 1,
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RQ24, 1,
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, 5,
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RQTY, 1,
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offset (0x1e84),
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, 15,
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SASR, 1, /* SATA 15 Shadow Reg Request Status Register */
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, 2,
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U2SR, 1, /* USB2 18 Shadow Reg Request Status Register */
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, 4,
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U3SR, 1, /* USB3 23 Shadow Reg Request Status Register */
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SDSR, 1, /* SD 24 Shadow Reg Request Status Register */
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offset (0x1e88),
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SRSA, 32, /* Shadow Reg SRAM Addr */
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SRSD, 32, /* Shadow Reg SRAM DATA */
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offset (0x1e94),
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SRDY, 1, /* S0i3 bios ready */
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offset (0x1ea0),
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PG1A, 1,
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PG2_, 1,
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,1,
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U3PG, 1, /* Usb3 Power Good BIT3 */
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offset (0x1ea3), /* Power Good Control */
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PGA3, 8 ,
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}
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OperationRegion(FCFG, SystemMemory, PCBA, 0x01000000)
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Field(FCFG, DwordAcc, NoLock, Preserve)
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{
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/* XHCI */
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Offset(0x00080010),
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XHBA, 32,
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Offset(0x0008002c),
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XH2C, 32,
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Offset(0x00080048),
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IDEX, 32,
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DATA, 32,
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Offset(0x00080054),
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U_PS, 2,
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/* SATA */
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Offset(0x00088010),
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ST10, 32,
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ST14, 32,
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ST18, 32,
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ST1C, 32,
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ST20, 32,
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ST24, 32,
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Offset(0x0008802c),
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ST2C, 32,
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Offset(0x00088040),
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ST40, 1,
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Offset(0x00088044),
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ST44, 1,
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Offset(0x0008804c),
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, 2,
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DDIC, 1, /* DisableDynamicInterfaceClockPowerSaving */
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Offset(0x00088064),
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S_PS, 2,
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Offset(0x00088084),
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, 1,
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ST84, 1,
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, 28,
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DSDN, 1, /* DShutDowN */
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Offset(0x0008808c),
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ST8C, 8,
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/* EHCI */
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Offset(0x00090004),
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, 1,
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EHME, 1,
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Offset(0x00090010),
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EHBA, 32,
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Offset(0x0009002c),
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EH2C, 32,
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Offset(0x00090054),
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EH54, 8,
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Offset(0x00090064),
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EH64, 8,
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Offset(0x000900c4),
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E_PS, 2,
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/* LPC Bridge */
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Offset(0x000a3078),
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, 2,
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LDQ0, 1,
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Offset(0x000a30cb),
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, 7,
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AUSS, 1, /* AutoSizeStart */
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/* SD */
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Offset(0x000a7004),
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, 1,
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SDME, 1,
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Offset(0x000a7010),
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SDBA, 32,
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Offset(0x000a702c),
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SD2C, 32,
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Offset(0x000a7094),
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D_PS, 2,
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, 6,
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SDPE, 1,
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, 6,
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PMES, 1,
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Offset(0x000a70b3), /* Version 2.0 = 0x1, Version 3.0 = 0x2 */
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SDB3, 8,
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Offset(0x000a70b4), /* Set Enable */
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, 8,
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SETE, 1,
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Offset(0x000a70d0),
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, 17,
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FC18, 1, /* Force 1.8v */
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}
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