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intel/apollolake: Move LPC decode enables to bootblock 

Doing this allows to call console_init() earlier in romstage.
This also fixes IO UART in bootblock, although it appears there
is currently no board that was affected.

Change-Id: Iec363a8c651cc1b05b24229db09d686938118f3a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34969
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-08-18 06:01:41 +03:00
parent 9172b6920c
commit b7908d2b08
2 changed files with 5 additions and 5 deletions
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3
src/soc/intel/apollolake/bootblock/bootblock.c
View File

@ -21,6 +21,7 @@
#include <device/pci_ops.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/p2sb.h>
#include <intelblocks/pcr.h>
#include <intelblocks/rtc.h>
@ -96,6 +97,8 @@ void bootblock_soc_early_init(void)
/* Prepare UART for serial console. */
if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
uart_bootblock_init();
if (CONFIG(DRIVERS_UART_8250IO))
lpc_io_setup_comm_a_b();
if (CONFIG(TPM_ON_FAST_SPI))
tpm_enable();

7
src/soc/intel/apollolake/romstage.c
View File

@ -91,9 +91,6 @@ static void soc_early_romstage_init(void)
/* Enable decoding for HPET. Needed for FSP global pointer storage */
pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
P2SB_HPTC_ADDRESS_ENABLE);
if (CONFIG(DRIVERS_UART_8250IO))
lpc_io_setup_comm_a_b();
}
/* Thermal throttle activation offset */
@ -207,10 +204,10 @@ asmlinkage void car_stage_entry(void)
timestamp_add_now(TS_START_ROMSTAGE);
soc_early_romstage_init();
console_init();
soc_early_romstage_init();
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake);