mainboard/volteer: Update Aux settings for Port 0
On Volteer port 0 (MB PORT) does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. This requires 2 changes setting the TcssAuxOri UPD to 1 for port 0 (Bit 0) and configuring AUXP and AUXN GPIOs to Native Function 6 so SOC can control the orientation BUG=b:145220205 BRANCH=NONE TEST=booted Volteer proto 2 and verified that the AUX channels flip when the cable is flipped Change-Id: Ic81adc24d10322cc305bf0fa4c38514468ea0942 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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@ -125,7 +125,16 @@ chip soc/intel/tigerlake
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# TCSS USB3
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register "TcssXhciEn" = "1"
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register "TcssAuxOri" = "0"
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register "TcssAuxOri" = "1"
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register "IomTypeCPortPadCfg[0]" = "0x090E000A"
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register "IomTypeCPortPadCfg[1]" = "0x090E000D"
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register "IomTypeCPortPadCfg[2]" = "0x0"
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register "IomTypeCPortPadCfg[3]" = "0x0"
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register "IomTypeCPortPadCfg[4]" = "0x0"
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register "IomTypeCPortPadCfg[5]" = "0x0"
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register "IomTypeCPortPadCfg[6]" = "0x0"
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register "IomTypeCPortPadCfg[7]" = "0x0"
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# DP port
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register "DdiPortAConfig" = "1" # eDP
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@ -215,13 +215,13 @@ static const struct pad_config gpio_table[] = {
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/* E9 : USB2_OC0# ==> USB_C1_OC_ODL */
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PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
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/* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */
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PAD_CFG_GPO(GPP_E10, 0, DEEP),
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PAD_CFG_NF(GPP_E10, NONE, DEEP, NF6),
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/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
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PAD_CFG_GPI(GPP_E11, NONE, DEEP),
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/* E12 : SPI1_MISO_IO1 ==> NOT USED */
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PAD_NC(GPP_E12, NONE),
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/* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */
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PAD_CFG_GPO(GPP_E13, 0, DEEP),
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PAD_CFG_NF(GPP_E13, NONE, DEEP, NF6),
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/* E14 : DDPC_HPDA ==> SOC_EDP_HPD */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
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