GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mainboard/volteer: Update Aux settings for Port 0 

On Volteer port 0 (MB PORT) does not have a retimer so the port needs
to be configured for the SOC to handle Aux orientation flipping. This
requires 2 changes setting the TcssAuxOri UPD to 1 for port 0 (Bit 0)
and configuring AUXP and AUXN GPIOs to Native Function 6 so SOC can
control the orientation

BUG=b:145220205
BRANCH=NONE
TEST=booted Volteer proto 2 and verified that the AUX channels flip
when the cable is flipped

Change-Id: Ic81adc24d10322cc305bf0fa4c38514468ea0942
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit is contained in:
Brandon Breitenstein 2020-04-06 15:34:19 -07:00 committed by Patrick Georgi
parent 71d365d458
commit b7911c8e98
2 changed files with 12 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
View File

@ -125,7 +125,16 @@ chip soc/intel/tigerlake
# TCSS USB3 # TCSS USB3
register "TcssXhciEn" = "1" register "TcssXhciEn" = "1"
register "TcssAuxOri" = "0" register "TcssAuxOri" = "1"
register "IomTypeCPortPadCfg[0]" = "0x090E000A"
register "IomTypeCPortPadCfg[1]" = "0x090E000D"
register "IomTypeCPortPadCfg[2]" = "0x0"
register "IomTypeCPortPadCfg[3]" = "0x0"
register "IomTypeCPortPadCfg[4]" = "0x0"
register "IomTypeCPortPadCfg[5]" = "0x0"
register "IomTypeCPortPadCfg[6]" = "0x0"
register "IomTypeCPortPadCfg[7]" = "0x0"
# DP port # DP port
register "DdiPortAConfig" = "1" # eDP register "DdiPortAConfig" = "1" # eDP

4
src/mainboard/google/volteer/variants/baseboard/gpio.c
View File

@ -215,13 +215,13 @@ static const struct pad_config gpio_table[] = {
/* E9 : USB2_OC0# ==> USB_C1_OC_ODL */ /* E9 : USB2_OC0# ==> USB_C1_OC_ODL */
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
/* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */ /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */
PAD_CFG_GPO(GPP_E10, 0, DEEP), PAD_CFG_NF(GPP_E10, NONE, DEEP, NF6),
/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
PAD_CFG_GPI(GPP_E11, NONE, DEEP), PAD_CFG_GPI(GPP_E11, NONE, DEEP),
/* E12 : SPI1_MISO_IO1 ==> NOT USED */ /* E12 : SPI1_MISO_IO1 ==> NOT USED */
PAD_NC(GPP_E12, NONE), PAD_NC(GPP_E12, NONE),
/* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */ /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */
PAD_CFG_GPO(GPP_E13, 0, DEEP), PAD_CFG_NF(GPP_E13, NONE, DEEP, NF6),
/* E14 : DDPC_HPDA ==> SOC_EDP_HPD */ /* E14 : DDPC_HPDA ==> SOC_EDP_HPD */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */