nb/intel/sandybridge/raminit: Add Kconfig option for fuses

Add a new Kconfig option to ignore memory fuses that limit the
maximum DRAM frequency to be used. The option is disabled by
default and should only enabled by experienced users as it
might decrease system stability or prevent a successful RAM
training.

Remove conflicting devicetree settings.

Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nicola Corna <nicola@corna.info>
This commit is contained in:
Patrick Rudolph 2017-08-08 13:13:51 +02:00 committed by Martin Roth
parent db27e3384a
commit b794a69ce9
12 changed files with 15 additions and 30 deletions

View File

@ -15,9 +15,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_up_delay" = "0"
register "gpu_pch_backlight" = "0x00000000"
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device cpu_cluster 0x0 on
chip cpu/intel/socket_rPGA989
device lapic 0x0 on

View File

@ -18,9 +18,6 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610"
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA988B
device lapic 0 on end

View File

@ -17,9 +17,6 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610"
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA988B
device lapic 0 on end

View File

@ -34,9 +34,6 @@ chip northbridge/intel/sandybridge
end
end
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device domain 0x0 on
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"

View File

@ -17,9 +17,6 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x11551155"
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end

View File

@ -18,9 +18,6 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610"
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA988B
device lapic 0 on end

View File

@ -18,9 +18,6 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x11551155"
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end

View File

@ -15,9 +15,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_up_delay" = "300"
register "gpu_pch_backlight" = "0x11551155"
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end

View File

@ -18,9 +18,6 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610"
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end

View File

@ -18,9 +18,6 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x11551155"
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end

View File

@ -44,6 +44,18 @@ config USE_NATIVE_RAMINIT
Select if you want to use coreboot implementation of raminit rather than
System Agent/MRC.bin. You should answer Y.
config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES
bool "Ignore vendor programmed fuses that limit max. DRAM frequency"
default n
depends on USE_NATIVE_RAMINIT
help
Ignore the mainboard's vendor programmed fuses that might limit the
maximum DRAM frequency. By selecting this option the fuses will be
ignored and the only limits on DRAM frequency are set by RAM's SPD and
hard fuses in southbridge's clockgen.
Disabled by default as it might causes system instability.
Handle with care!
config CBFS_SIZE
hex
default 0x100000

View File

@ -402,6 +402,9 @@ unsigned int get_mem_min_tck(void)
/* If this is zero, it just means devicetree.cb didn't set it */
if (!cfg || cfg->max_mem_clock_mhz == 0) {
if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))
return TCK_1333MHZ;
rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {