nb/intel/sandybridge/raminit: Add Kconfig option for fuses
Add a new Kconfig option to ignore memory fuses that limit the maximum DRAM frequency to be used. The option is disabled by default and should only enabled by experienced users as it might decrease system stability or prevent a successful RAM training. Remove conflicting devicetree settings. Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nicola Corna <nicola@corna.info>
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@ -15,9 +15,6 @@ chip northbridge/intel/sandybridge
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register "gpu_panel_power_up_delay" = "0"
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register "gpu_pch_backlight" = "0x00000000"
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# Override fuse bits that hard-code the value to 666 Mhz
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register "max_mem_clock_mhz" = "933"
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device cpu_cluster 0x0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0x0 on
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@ -18,9 +18,6 @@ chip northbridge/intel/sandybridge
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register "gpu_cpu_backlight" = "0x1155"
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register "gpu_pch_backlight" = "0x06100610"
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# Override fuse bits that hard-code the value to 666 Mhz
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register "max_mem_clock_mhz" = "933"
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA988B
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device lapic 0 on end
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@ -17,9 +17,6 @@ chip northbridge/intel/sandybridge
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register "gpu_cpu_backlight" = "0x1155"
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register "gpu_pch_backlight" = "0x06100610"
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# Override fuse bits that hard-code the value to 666 Mhz
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register "max_mem_clock_mhz" = "933"
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA988B
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device lapic 0 on end
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@ -34,9 +34,6 @@ chip northbridge/intel/sandybridge
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end
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end
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# Override fuse bits that hard-code the value to 666 Mhz
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register "max_mem_clock_mhz" = "933"
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device domain 0x0 on
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "c2_latency" = "0x0065"
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@ -17,9 +17,6 @@ chip northbridge/intel/sandybridge
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register "gpu_cpu_backlight" = "0x1155"
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register "gpu_pch_backlight" = "0x11551155"
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# Override fuse bits that hard-code the value to 666 Mhz
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register "max_mem_clock_mhz" = "933"
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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@ -18,9 +18,6 @@ chip northbridge/intel/sandybridge
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register "gpu_cpu_backlight" = "0x1155"
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register "gpu_pch_backlight" = "0x06100610"
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# Override fuse bits that hard-code the value to 666 Mhz
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register "max_mem_clock_mhz" = "933"
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA988B
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device lapic 0 on end
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@ -18,9 +18,6 @@ chip northbridge/intel/sandybridge
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register "gpu_cpu_backlight" = "0x1155"
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register "gpu_pch_backlight" = "0x11551155"
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# Override fuse bits that hard-code the value to 666 Mhz
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register "max_mem_clock_mhz" = "933"
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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@ -15,9 +15,6 @@ chip northbridge/intel/sandybridge
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register "gpu_panel_power_up_delay" = "300"
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register "gpu_pch_backlight" = "0x11551155"
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# Override fuse bits that hard-code the value to 666 Mhz
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register "max_mem_clock_mhz" = "933"
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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@ -18,9 +18,6 @@ chip northbridge/intel/sandybridge
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register "gpu_cpu_backlight" = "0x1155"
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register "gpu_pch_backlight" = "0x06100610"
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# Override fuse bits that hard-code the value to 666 Mhz
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register "max_mem_clock_mhz" = "933"
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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@ -18,9 +18,6 @@ chip northbridge/intel/sandybridge
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register "gpu_cpu_backlight" = "0x1155"
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register "gpu_pch_backlight" = "0x11551155"
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# Override fuse bits that hard-code the value to 666 Mhz
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register "max_mem_clock_mhz" = "933"
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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@ -44,6 +44,18 @@ config USE_NATIVE_RAMINIT
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Select if you want to use coreboot implementation of raminit rather than
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System Agent/MRC.bin. You should answer Y.
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config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES
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bool "Ignore vendor programmed fuses that limit max. DRAM frequency"
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default n
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depends on USE_NATIVE_RAMINIT
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help
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Ignore the mainboard's vendor programmed fuses that might limit the
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maximum DRAM frequency. By selecting this option the fuses will be
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ignored and the only limits on DRAM frequency are set by RAM's SPD and
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hard fuses in southbridge's clockgen.
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Disabled by default as it might causes system instability.
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Handle with care!
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config CBFS_SIZE
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hex
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default 0x100000
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@ -402,6 +402,9 @@ unsigned int get_mem_min_tck(void)
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/* If this is zero, it just means devicetree.cb didn't set it */
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if (!cfg || cfg->max_mem_clock_mhz == 0) {
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if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))
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return TCK_1333MHZ;
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rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
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if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
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