mb/google/puff: Convert ASL file to new DPTF dt impl

This patch converts the current DPTF policies from static ASL files into
the new SSDT-based DPTF implementation. All settings are intended to be
copied exactly.

BUG=b:158986928
BRANCH=puff
TEST=duffy boots and dumped SSDT table for quick check.

Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/mainboard/google/hatch/Kconfig

@@ -12,6 +12,8 @@ config BOARD_GOOGLE_BASEBOARD_PUFF
 	select ROMSTAGE_SPD_SMBUS
 	select SPD_READ_BY_WORD
 	select SOC_INTEL_CSE_LITE_SKU
+	select DRIVERS_INTEL_DPTF
+	select DPTF_USE_EISA_HID
 
 config BOARD_GOOGLE_HATCH_COMMON
 	def_bool n
@@ -38,6 +40,7 @@ config BOARD_GOOGLE_HATCH_COMMON
 	select MAINBOARD_HAS_TPM2
 	select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
 	select SOC_INTEL_COMETLAKE
+	select SOC_INTEL_COMMON_BLOCK_DTT
 
 if BOARD_GOOGLE_HATCH_COMMON
 

src/mainboard/google/hatch/dsdt.asl

@@ -48,6 +48,7 @@ DefinitionBlock(
 		#include <ec/google/chromeec/acpi/ec.asl>
 	}
 
+#if CONFIG(BOARD_GOOGLE_BASEBOARD_HATCH)
 	/* Dynamic Platform Thermal Framework */
 	Scope (\_SB)
 	{
@@ -56,4 +57,5 @@ DefinitionBlock(
 		/* Include common dptf ASL files */
 		#include <soc/intel/common/acpi/dptf/dptf.asl>
 	}
+#endif
 }

src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl

@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#define DPTF_CPU_PASSIVE	93
-#define DPTF_CPU_CRITICAL	100
-#define DPTF_CPU_ACTIVE_AC0	90
-#define DPTF_CPU_ACTIVE_AC1	85
-#define DPTF_CPU_ACTIVE_AC2	80
-#define DPTF_CPU_ACTIVE_AC3	75
-#define DPTF_CPU_ACTIVE_AC4	70
-#define DPTF_CPU_ACTIVE_AC5	65
-
-#define DPTF_TSR0_SENSOR_ID	0
-#define DPTF_TSR0_SENSOR_NAME	"Thermal Sensor 1"
-#define DPTF_TSR0_PASSIVE	65
-#define DPTF_TSR0_CRITICAL	75
-#define DPTF_TSR0_ACTIVE_AC0	50
-#define DPTF_TSR0_ACTIVE_AC1	47
-#define DPTF_TSR0_ACTIVE_AC2	45
-#define DPTF_TSR0_ACTIVE_AC3	42
-#define DPTF_TSR0_ACTIVE_AC4	39
-
-#define DPTF_ENABLE_CHARGER
-#define DPTF_ENABLE_FAN_CONTROL
-
-/* Charger performance states, board-specific values from charger and EC */
-Name (CHPS, Package () {
-	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
-	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
-	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
-	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
-})
-
-/* DFPS: Fan Performance States */
-Name (DFPS, Package () {
-	0,	// Revision
-	/*
-	 * TODO : Need to update this Table after characterization.
-	 *	  These are initial reference values.
-	 */
-	/* Control, Trip Point, Speed, NoiseLevel, Power */
-	Package () {90,		0xFFFFFFFF,	6700,	220,	2200},
-	Package () {80,		0xFFFFFFFF,	5800,	180,	1800},
-	Package () {70,		0xFFFFFFFF,	5000,	145,	1450},
-	Package () {60,		0xFFFFFFFF,	4900,	115,	1150},
-	Package () {50,		0xFFFFFFFF,	3838,	90,	900},
-	Package () {40,		0xFFFFFFFF,	2904,	55,	550},
-	Package () {30,		0xFFFFFFFF,	2337,	30,	300},
-	Package () {20,		0xFFFFFFFF,	1608,	15,	150},
-	Package () {10,		0xFFFFFFFF,	800,	10,	100},
-	Package () {0,		0xFFFFFFFF,	0,	0,	50}
-})
-
-Name (DART, Package () {
-	/* Fan effect on CPU */
-	0,	// Revision
-	Package () {
-		/*
-		 * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
-		 *	AC7, AC8, AC9
-		 */
-		\_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 95, 85, 75, 65, 55, 45, 0, 0,
-			0, 0, 0
-	},
-	Package () {
-		\_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 95, 85, 75, 65, 55, 45, 0, 0,
-			0, 0, 0
-	}
-})
-
-Name (DTRT, Package () {
-	/* CPU Throttle Effect on CPU */
-	Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
-
-	/* CPU Throttle Effect on Ambient (TSR0) */
-	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 },
-})
-
-Name (MPPC, Package ()
-{
-	0x2,		/* Revision */
-	Package () {	/* Power Limit 1 */
-		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
-		15000,	/* PowerLimitMinimum */
-		15000,	/* PowerLimitMaximum */
-		28000,	/* TimeWindowMinimum */
-		32000,	/* TimeWindowMaximum */
-		200	/* StepSize */
-	},
-	Package () {	/* Power Limit 2 */
-		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
-		25000,	/* PowerLimitMinimum */
-		64000,	/* PowerLimitMaximum */
-		28000,	/* TimeWindowMinimum */
-		32000,	/* TimeWindowMaximum */
-		1000	/* StepSize */
-	}
-})

src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl

@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <puff/acpi/dptf.asl>

src/mainboard/google/hatch/variants/duffy/overridetree.cb

@@ -267,6 +267,71 @@ chip soc/intel/cannonlake
 	register "sata_port[1].TxGen3DeEmph" = "0x20"
 
 	device domain 0 on
+		device pci 04.0 on
+			chip drivers/intel/dptf
+				## Active Policy
+				register "policies.active[0]" = "{.target=DPTF_CPU,
+					.thresholds={TEMP_PCT(90, 85),
+						     TEMP_PCT(85, 75),
+						     TEMP_PCT(80, 65),
+						     TEMP_PCT(75, 55),
+						     TEMP_PCT(70, 45),}}"
+				register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
+					.thresholds={TEMP_PCT(50, 85),
+						     TEMP_PCT(47, 75),
+						     TEMP_PCT(45, 65),
+						     TEMP_PCT(42, 55),
+						     TEMP_PCT(39, 45),}}"
+
+				## Passive Policy
+				register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU,           93, 5000)"
+				register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)"
+
+				## Critical Policy
+				register "policies.critical[0]" = "DPTF_CRITICAL(CPU,          100, SHUTDOWN)"
+				register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)"
+
+				## Power Limits Control
+				# PL1 is fixed at 15W, avg over 28-32s interval
+				# 25-64W PL2 in 1000mW increments, avg over 28-32s interval
+				register "controls.power_limits.pl1" = "{
+					.min_power = 15000,
+					.max_power = 15000,
+					.time_window_min = 28 * MSECS_PER_SEC,
+					.time_window_max = 32 * MSECS_PER_SEC,
+					.granularity = 200,}"
+				register "controls.power_limits.pl2" = "{
+					.min_power = 25000,
+					.max_power = 64000,
+					.time_window_min = 28 * MSECS_PER_SEC,
+					.time_window_max = 32 * MSECS_PER_SEC,
+					.granularity = 1000,}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf[0]" = "{ 255, 1700 }"
+				register "controls.charger_perf[1]" = "{  24, 1500 }"
+				register "controls.charger_perf[2]" = "{  16, 1000 }"
+				register "controls.charger_perf[3]" = "{   8,  500 }"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf[0]" = "{  90, 6700, 220, 2200, }"
+				register "controls.fan_perf[1]" = "{  80, 5800, 180, 1800, }"
+				register "controls.fan_perf[2]" = "{  70, 5000, 145, 1450, }"
+				register "controls.fan_perf[3]" = "{  60, 4900, 115, 1150, }"
+				register "controls.fan_perf[4]" = "{  50, 3838,  90,  900, }"
+				register "controls.fan_perf[5]" = "{  40, 2904,  55,  550, }"
+				register "controls.fan_perf[6]" = "{  30, 2337,  30,  300, }"
+				register "controls.fan_perf[7]" = "{  20, 1608,  15,  150, }"
+				register "controls.fan_perf[8]" = "{  10,  800,  10,  100, }"
+				register "controls.fan_perf[9]" = "{   0,    0,   0,   50, }"
+
+				# Fan options
+				register "options.fan.fine_grained_control" = "1"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 on end
+			end
+		end # DPTF 0x1903
 		device pci 14.0 on
 			chip drivers/usb/acpi
 				device usb 0.0 on

src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl

@@ -1,86 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#define DPTF_CPU_PASSIVE	90
-#define DPTF_CPU_CRITICAL	100
-
-#define DPTF_TSR0_SENSOR_ID	0
-#define DPTF_TSR0_SENSOR_NAME	"Thermal Sensor 1"
-#define DPTF_TSR0_PASSIVE	60
-#define DPTF_TSR0_CRITICAL	85
-
-#define DPTF_ENABLE_CHARGER
-#define DPTF_ENABLE_FAN_CONTROL
-
-/* Charger performance states, board-specific values from charger and EC */
-Name (CHPS, Package () {
-	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
-	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
-	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
-	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
-})
-
-/* DFPS: Fan Performance States */
-Name (DFPS, Package () {
-	0,	// Revision
-	/*
-	 * TODO : Need to update this Table after characterization.
-	 *	  These are initial reference values.
-	 */
-	/* Control, Trip Point, Speed, NoiseLevel, Power */
-	Package () {90,		0xFFFFFFFF,	6700,	220,	2200},
-	Package () {80,		0xFFFFFFFF,	5800,	180,	1800},
-	Package () {70,		0xFFFFFFFF,	5000,	145,	1450},
-	Package () {60,		0xFFFFFFFF,	4900,	115,	1150},
-	Package () {50,		0xFFFFFFFF,	3838,	90,	900},
-	Package () {40,		0xFFFFFFFF,	2904,	55,	550},
-	Package () {30,		0xFFFFFFFF,	2337,	30,	300},
-	Package () {20,		0xFFFFFFFF,	1608,	15,	150},
-	Package () {10,		0xFFFFFFFF,	800,	10,	100},
-	Package () {0,		0xFFFFFFFF,	0,	0,	50}
-})
-
-Name (DART, Package () {
-	/* Fan effect on CPU */
-	0,	// Revision
-	Package () {
-		/*
-		 * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
-		 *	AC7, AC8, AC9
-		 */
-		\_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 95, 85, 75, 65, 55, 45, 0, 0,
-			0, 0, 0
-	},
-	Package () {
-		\_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 95, 85, 75, 65, 55, 45, 0, 0,
-			0, 0, 0
-	}
-})
-
-Name (DTRT, Package () {
-	/* CPU Throttle Effect on CPU */
-	Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
-
-	/* CPU Throttle Effect on Ambient (TSR0) */
-	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 },
-})
-
-Name (MPPC, Package ()
-{
-	0x2,		/* Revision */
-	Package () {	/* Power Limit 1 */
-		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
-		10000,	/* PowerLimitMinimum */
-		15000,	/* PowerLimitMaximum */
-		28000,	/* TimeWindowMinimum */
-		32000,	/* TimeWindowMaximum */
-		200	/* StepSize */
-	},
-	Package () {	/* Power Limit 2 */
-		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
-		25000,	/* PowerLimitMinimum */
-		51000,	/* PowerLimitMaximum */
-		28000,	/* TimeWindowMinimum */
-		32000,	/* TimeWindowMaximum */
-		1000	/* StepSize */
-	}
-})

src/mainboard/google/hatch/variants/faffy/overridetree.cb

@@ -273,6 +273,41 @@ chip soc/intel/cannonlake
 	register "sata_port[1].TxGen3DeEmph" = "0x20"
 
 	device domain 0 on
+		device pci 04.0 on
+			chip drivers/intel/dptf
+				## Passive Policy
+				register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 5000)"
+				register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 60, 5000)"
+
+				## Critical Policy
+				register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)"
+				register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)"
+
+				## Power Limits Control
+				# 10-15W PL1 in 200mW increments, avg over 28-32s interval
+				# 25-51W PL2 in 1000mW increments, avg over 28-32s interval
+				register "controls.power_limits.pl1" = "{
+					.min_power = 10000,
+					.max_power = 15000,
+					.time_window_min = 28 * MSECS_PER_SEC,
+					.time_window_max = 32 * MSECS_PER_SEC,
+					.granularity = 200,}"
+				register "controls.power_limits.pl2" = "{
+					.min_power = 25000,
+					.max_power = 51000,
+					.time_window_min = 28 * MSECS_PER_SEC,
+					.time_window_max = 32 * MSECS_PER_SEC,
+					.granularity = 1000,}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf[0]" = "{ 255, 1700 }"
+				register "controls.charger_perf[1]" = "{  24, 1500 }"
+				register "controls.charger_perf[2]" = "{  16, 1000 }"
+				register "controls.charger_perf[3]" = "{   8,  500 }"
+
+				device generic 0 on end
+			end
+		end # DPTF 0x1903
 		device pci 14.0 on
 			chip drivers/usb/acpi
 				device usb 0.0 on

src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl

@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <puff/acpi/dptf.asl>

src/mainboard/google/hatch/variants/kaisa/overridetree.cb

@@ -267,6 +267,71 @@ chip soc/intel/cannonlake
 	register "sata_port[1].TxGen3DeEmph" = "0x20"
 
 	device domain 0 on
+		device pci 04.0 on
+			chip drivers/intel/dptf
+				## Active Policy
+				register "policies.active[0]" = "{.target=DPTF_CPU,
+					.thresholds={TEMP_PCT(90, 85),
+						     TEMP_PCT(85, 75),
+						     TEMP_PCT(80, 65),
+						     TEMP_PCT(75, 55),
+						     TEMP_PCT(70, 45),}}"
+				register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
+					.thresholds={TEMP_PCT(50, 85),
+						     TEMP_PCT(47, 75),
+						     TEMP_PCT(45, 65),
+						     TEMP_PCT(42, 55),
+						     TEMP_PCT(39, 45),}}"
+
+				## Passive Policy
+				register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU,           93, 5000)"
+				register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)"
+
+				## Critical Policy
+				register "policies.critical[0]" = "DPTF_CRITICAL(CPU,          100, SHUTDOWN)"
+				register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)"
+
+				## Power Limits Control
+				# PL1 is fixed at 15W, avg over 28-32s interval
+				# 25-64W PL2 in 1000mW increments, avg over 28-32s interval
+				register "controls.power_limits.pl1" = "{
+					.min_power = 15000,
+					.max_power = 15000,
+					.time_window_min = 28 * MSECS_PER_SEC,
+					.time_window_max = 32 * MSECS_PER_SEC,
+					.granularity = 200,}"
+				register "controls.power_limits.pl2" = "{
+					.min_power = 25000,
+					.max_power = 64000,
+					.time_window_min = 28 * MSECS_PER_SEC,
+					.time_window_max = 32 * MSECS_PER_SEC,
+					.granularity = 1000,}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf[0]" = "{ 255, 1700 }"
+				register "controls.charger_perf[1]" = "{  24, 1500 }"
+				register "controls.charger_perf[2]" = "{  16, 1000 }"
+				register "controls.charger_perf[3]" = "{   8,  500 }"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf[0]" = "{  90, 6700, 220, 2200, }"
+				register "controls.fan_perf[1]" = "{  80, 5800, 180, 1800, }"
+				register "controls.fan_perf[2]" = "{  70, 5000, 145, 1450, }"
+				register "controls.fan_perf[3]" = "{  60, 4900, 115, 1150, }"
+				register "controls.fan_perf[4]" = "{  50, 3838,  90,  900, }"
+				register "controls.fan_perf[5]" = "{  40, 2904,  55,  550, }"
+				register "controls.fan_perf[6]" = "{  30, 2337,  30,  300, }"
+				register "controls.fan_perf[7]" = "{  20, 1608,  15,  150, }"
+				register "controls.fan_perf[8]" = "{  10,  800,  10,  100, }"
+				register "controls.fan_perf[9]" = "{   0,    0,   0,   50, }"
+
+				# Fan options
+				register "options.fan.fine_grained_control" = "1"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 on end
+			end
+		end # DPTF 0x1903
 		device pci 14.0 on
 			chip drivers/usb/acpi
 				device usb 0.0 on

src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl

@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <puff/acpi/dptf.asl>

src/mainboard/google/hatch/variants/noibat/overridetree.cb

@@ -193,6 +193,71 @@ chip soc/intel/cannonlake
 	register "sata_port[1].TxGen3DeEmph" = "0x20"
 
 	device domain 0 on
+		device pci 04.0 on
+			chip drivers/intel/dptf
+				## Active Policy
+				register "policies.active[0]" = "{.target=DPTF_CPU,
+					.thresholds={TEMP_PCT(90, 85),
+						     TEMP_PCT(85, 75),
+						     TEMP_PCT(80, 65),
+						     TEMP_PCT(75, 55),
+						     TEMP_PCT(70, 45),}}"
+				register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
+					.thresholds={TEMP_PCT(50, 85),
+						     TEMP_PCT(47, 75),
+						     TEMP_PCT(45, 65),
+						     TEMP_PCT(42, 55),
+						     TEMP_PCT(39, 45),}}"
+
+				## Passive Policy
+				register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU,           93, 5000)"
+				register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)"
+
+				## Critical Policy
+				register "policies.critical[0]" = "DPTF_CRITICAL(CPU,          100, SHUTDOWN)"
+				register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)"
+
+				## Power Limits Control
+				# PL1 is fixed at 15W, avg over 28-32s interval
+				# 25-64W PL2 in 1000mW increments, avg over 28-32s interval
+				register "controls.power_limits.pl1" = "{
+					.min_power = 15000,
+					.max_power = 15000,
+					.time_window_min = 28 * MSECS_PER_SEC,
+					.time_window_max = 32 * MSECS_PER_SEC,
+					.granularity = 200,}"
+				register "controls.power_limits.pl2" = "{
+					.min_power = 25000,
+					.max_power = 64000,
+					.time_window_min = 28 * MSECS_PER_SEC,
+					.time_window_max = 32 * MSECS_PER_SEC,
+					.granularity = 1000,}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf[0]" = "{ 255, 1700 }"
+				register "controls.charger_perf[1]" = "{  24, 1500 }"
+				register "controls.charger_perf[2]" = "{  16, 1000 }"
+				register "controls.charger_perf[3]" = "{   8,  500 }"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf[0]" = "{  90, 6700, 220, 2200, }"
+				register "controls.fan_perf[1]" = "{  80, 5800, 180, 1800, }"
+				register "controls.fan_perf[2]" = "{  70, 5000, 145, 1450, }"
+				register "controls.fan_perf[3]" = "{  60, 4900, 115, 1150, }"
+				register "controls.fan_perf[4]" = "{  50, 3838,  90,  900, }"
+				register "controls.fan_perf[5]" = "{  40, 2904,  55,  550, }"
+				register "controls.fan_perf[6]" = "{  30, 2337,  30,  300, }"
+				register "controls.fan_perf[7]" = "{  20, 1608,  15,  150, }"
+				register "controls.fan_perf[8]" = "{  10,  800,  10,  100, }"
+				register "controls.fan_perf[9]" = "{   0,    0,   0,   50, }"
+
+				# Fan options
+				register "options.fan.fine_grained_control" = "1"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 on end
+			end
+		end # DPTF 0x1903
 		device pci 14.0 on
 			chip drivers/usb/acpi
 				device usb 0.0 on

src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl

@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <puff/acpi/dptf.asl>

src/mainboard/google/hatch/variants/puff/overridetree.cb

@@ -205,6 +205,71 @@ chip soc/intel/cannonlake
 	register "sata_port[1].TxGen3DeEmph" = "0x20"
 
 	device domain 0 on
+		device pci 04.0 on
+			chip drivers/intel/dptf
+				## Active Policy
+				register "policies.active[0]" = "{.target=DPTF_CPU,
+					.thresholds={TEMP_PCT(90, 85),
+						     TEMP_PCT(85, 75),
+						     TEMP_PCT(80, 65),
+						     TEMP_PCT(75, 55),
+						     TEMP_PCT(70, 45),}}"
+				register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
+					.thresholds={TEMP_PCT(50, 85),
+						     TEMP_PCT(47, 75),
+						     TEMP_PCT(45, 65),
+						     TEMP_PCT(42, 55),
+						     TEMP_PCT(39, 45),}}"
+
+				## Passive Policy
+				register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU,           93, 5000)"
+				register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)"
+
+				## Critical Policy
+				register "policies.critical[0]" = "DPTF_CRITICAL(CPU,          100, SHUTDOWN)"
+				register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)"
+
+				## Power Limits Control
+				# PL1 is fixed at 15W, avg over 28-32s interval
+				# 25-64W PL2 in 1000mW increments, avg over 28-32s interval
+				register "controls.power_limits.pl1" = "{
+					.min_power = 15000,
+					.max_power = 15000,
+					.time_window_min = 28 * MSECS_PER_SEC,
+					.time_window_max = 32 * MSECS_PER_SEC,
+					.granularity = 200,}"
+				register "controls.power_limits.pl2" = "{
+					.min_power = 25000,
+					.max_power = 64000,
+					.time_window_min = 28 * MSECS_PER_SEC,
+					.time_window_max = 32 * MSECS_PER_SEC,
+					.granularity = 1000,}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf[0]" = "{ 255, 1700 }"
+				register "controls.charger_perf[1]" = "{  24, 1500 }"
+				register "controls.charger_perf[2]" = "{  16, 1000 }"
+				register "controls.charger_perf[3]" = "{   8,  500 }"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf[0]" = "{  90, 6700, 220, 2200, }"
+				register "controls.fan_perf[1]" = "{  80, 5800, 180, 1800, }"
+				register "controls.fan_perf[2]" = "{  70, 5000, 145, 1450, }"
+				register "controls.fan_perf[3]" = "{  60, 4900, 115, 1150, }"
+				register "controls.fan_perf[4]" = "{  50, 3838,  90,  900, }"
+				register "controls.fan_perf[5]" = "{  40, 2904,  55,  550, }"
+				register "controls.fan_perf[6]" = "{  30, 2337,  30,  300, }"
+				register "controls.fan_perf[7]" = "{  20, 1608,  15,  150, }"
+				register "controls.fan_perf[8]" = "{  10,  800,  10,  100, }"
+				register "controls.fan_perf[9]" = "{   0,    0,   0,   50, }"
+
+				# Fan options
+				register "options.fan.fine_grained_control" = "1"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 on end
+			end
+		end # DPTF 0x1903
 		device pci 14.0 on
 			chip drivers/usb/acpi
 				device usb 0.0 on

src/mainboard/google/hatch/variants/wyvern/include/variant/acpi/dptf.asl

@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <puff/acpi/dptf.asl>

src/mainboard/google/hatch/variants/wyvern/overridetree.cb

@@ -200,6 +200,71 @@ chip soc/intel/cannonlake
 	register "sata_port[1].TxGen3DeEmph" = "0x20"
 
 	device domain 0 on
+		device pci 04.0 on
+			chip drivers/intel/dptf
+				## Active Policy
+				register "policies.active[0]" = "{.target=DPTF_CPU,
+					.thresholds={TEMP_PCT(90, 85),
+						     TEMP_PCT(85, 75),
+						     TEMP_PCT(80, 65),
+						     TEMP_PCT(75, 55),
+						     TEMP_PCT(70, 45),}}"
+				register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
+					.thresholds={TEMP_PCT(50, 85),
+						     TEMP_PCT(47, 75),
+						     TEMP_PCT(45, 65),
+						     TEMP_PCT(42, 55),
+						     TEMP_PCT(39, 45),}}"
+
+				## Passive Policy
+				register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU,           93, 5000)"
+				register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)"
+
+				## Critical Policy
+				register "policies.critical[0]" = "DPTF_CRITICAL(CPU,          100, SHUTDOWN)"
+				register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)"
+
+				## Power Limits Control
+				# PL1 is fixed at 15W, avg over 28-32s interval
+				# 25-64W PL2 in 1000mW increments, avg over 28-32s interval
+				register "controls.power_limits.pl1" = "{
+					.min_power = 15000,
+					.max_power = 15000,
+					.time_window_min = 28 * MSECS_PER_SEC,
+					.time_window_max = 32 * MSECS_PER_SEC,
+					.granularity = 200,}"
+				register "controls.power_limits.pl2" = "{
+					.min_power = 25000,
+					.max_power = 64000,
+					.time_window_min = 28 * MSECS_PER_SEC,
+					.time_window_max = 32 * MSECS_PER_SEC,
+					.granularity = 1000,}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf[0]" = "{ 255, 1700 }"
+				register "controls.charger_perf[1]" = "{  24, 1500 }"
+				register "controls.charger_perf[2]" = "{  16, 1000 }"
+				register "controls.charger_perf[3]" = "{   8,  500 }"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf[0]" = "{  90, 6700, 220, 2200, }"
+				register "controls.fan_perf[1]" = "{  80, 5800, 180, 1800, }"
+				register "controls.fan_perf[2]" = "{  70, 5000, 145, 1450, }"
+				register "controls.fan_perf[3]" = "{  60, 4900, 115, 1150, }"
+				register "controls.fan_perf[4]" = "{  50, 3838,  90,  900, }"
+				register "controls.fan_perf[5]" = "{  40, 2904,  55,  550, }"
+				register "controls.fan_perf[6]" = "{  30, 2337,  30,  300, }"
+				register "controls.fan_perf[7]" = "{  20, 1608,  15,  150, }"
+				register "controls.fan_perf[8]" = "{  10,  800,  10,  100, }"
+				register "controls.fan_perf[9]" = "{   0,    0,   0,   50, }"
+
+				# Fan options
+				register "options.fan.fine_grained_control" = "1"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 on end
+			end
+		end # DPTF 0x1903
 		device pci 14.0 on
 			chip drivers/usb/acpi
 				device usb 0.0 on