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don't enable VGA/ISA here, it is done in device.c:allocate_vga_resource 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo 2004-05-13 20:40:12 +00:00
parent 6a8745ae57
commit b7ae8cf8a3
1 changed files with 23 additions and 35 deletions
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58
src/southbridge/amd/amd8151/amd8151_agp3.c
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@ -13,56 +13,45 @@ static void agp3bridge_init(device_t dev)
{ {
uint8_t byte; uint8_t byte;
/* Enable BM and IO */ /* Enable BM, MEM and IO */
byte = pci_read_config32(dev, 0x04); byte = pci_read_config32(dev, 0x04);
byte |= 0x07; byte |= 0x07;
pci_write_config8(dev, 0x04, byte); pci_write_config8(dev, 0x04, byte);
/* Eable VGA/ISA decoding */
byte = pci_read_config32(dev, 0x3e);
byte |= 3<<2;
pci_write_config8(dev, 0x3e, byte);
return; return;
} }
static struct device_operations agp3bridge_ops = { static struct device_operations agp3bridge_ops = {
.read_resources = pci_bus_read_resources, .read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources, .enable_resources = pci_bus_enable_resources,
.init = agp3bridge_init, .init = agp3bridge_init,
.scan_bus = pci_scan_bridge, .scan_bus = pci_scan_bridge,
}; };
static struct pci_driver agp3bridge_driver __pci_driver = { static struct pci_driver agp3bridge_driver __pci_driver = {
.ops = &agp3bridge_ops, .ops = &agp3bridge_ops,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VENDOR_ID_AMD,
.device = 0x7455, // AGP Bridge .device = 0x7455, // AGP Bridge
}; };
static void agp3dev_enable(device_t dev) static void agp3dev_enable(device_t dev)
{ {
uint32_t value; uint32_t value;
// AGP enable /* AGP enable */
value = pci_read_config32(dev, 0xa8); value = pci_read_config32(dev, 0xa8);
value |= (3<<8)|2; //AGP 8x value |= (3<<8)|2; //AGP 8x
pci_write_config32(dev, 0xa8, value); pci_write_config32(dev, 0xa8, value);
/*
// linkA 8bit-->16bit
value = pci_read_config32(dev, 0xc4);
value |= (0x11<<24);
pci_write_config32(dev, 0xc4, value);
// linkA 200-->600 /* enable BM and MEM */
value = pci_read_config32(dev, 0xcc); value = pci_read_config32(dev, 0x4);
value |= (4<<8); value |= 6;
pci_write_config32(dev, 0xcc, value); pci_write_config32(dev, 0x4, value);
*/ #if 0
/* FIXME: should we add agp aperture base and size here ?
value = pci_read_config32(dev, 0x4); * or it is done by AGP drivers */
value |= 6; #endif
pci_write_config32(dev, 0x4, value);
} }
static struct device_operations agp3dev_ops = { static struct device_operations agp3dev_ops = {
@ -77,6 +66,5 @@ static struct device_operations agp3dev_ops = {
static struct pci_driver agp3dev_driver __pci_driver = { static struct pci_driver agp3dev_driver __pci_driver = {
.ops = &agp3dev_ops, .ops = &agp3dev_ops,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VENDOR_ID_AMD,
.device = 0x7454, //AGP Device .device = 0x7454, //AGP Device
}; };