soc/intel/apollolake: Make use of Intel common Graphics block
TEST=Build and boot reef. Change-Id: I0edd7454912201598c43e35990e470ec18a32638 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -71,6 +71,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES
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select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
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select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY
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select SOC_INTEL_COMMON_BLOCK_GRAPHICS
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select SOC_INTEL_COMMON_BLOCK_ITSS
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select SOC_INTEL_COMMON_BLOCK_I2C
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select SOC_INTEL_COMMON_BLOCK_LPC
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Intel Corp.
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* Copyright (C) 2015-2017 Intel Corp.
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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@ -15,34 +15,21 @@
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include <console/console.h>
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#include <fsp/util.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <soc/pci_devs.h>
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#include <intelblocks/graphics.h>
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#include <soc/intel/common/opregion.h>
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uintptr_t fsp_soc_get_igd_bar(void)
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{
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device_t dev = SA_DEV_IGD;
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/* Check if IGD PCI device is disabled */
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if (!dev->enabled)
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return 0;
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return find_resource(dev, PCI_BASE_ADDRESS_2)->base;
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return graphics_get_memory_base();
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}
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static void igd_set_resources(struct device *dev)
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{
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pci_dev_set_resources(dev);
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}
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static unsigned long igd_write_opregion(device_t dev, unsigned long current,
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struct acpi_rsdp *rsdp)
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uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
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uintptr_t current, struct acpi_rsdp *rsdp)
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{
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igd_opregion_t *opregion;
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uint16_t reg16;
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@ -77,34 +64,11 @@ static unsigned long igd_write_opregion(device_t dev, unsigned long current,
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* Maybe it should move to the finalize handler.
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*/
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pci_write_config32(dev, ASLS, (uintptr_t)opregion);
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reg16 = pci_read_config16(dev, SWSCI);
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pci_write_config32(device, ASLS, (uintptr_t)opregion);
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reg16 = pci_read_config16(device, SWSCI);
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reg16 &= ~(1 << 0);
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reg16 |= (1 << 15);
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pci_write_config16(dev, SWSCI, reg16);
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pci_write_config16(device, SWSCI, reg16);
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return acpi_align_current(current);
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}
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static const struct device_operations igd_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = igd_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = pci_dev_init,
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.write_acpi_tables = igd_write_opregion,
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.enable = DEVICE_NOOP
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_APL_IGD_HD_505,
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PCI_DEVICE_ID_INTEL_APL_IGD_HD_500,
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PCI_DEVICE_ID_INTEL_GLK_IGD,
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PCI_DEVICE_ID_INTEL_GLK_IGD_EU12,
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0,
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};
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static const struct pci_driver integrated_graphics_driver __pci_driver = {
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.ops = &igd_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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