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Enable SPI cacheline prefetch early to reduce boot time. 

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Scott Duplichan 2011-05-15 21:56:03 +00:00 committed by Marc Jones
parent 2cc5f550c7
commit b7e068305c
1 changed files with 15 additions and 11 deletions
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26
src/mainboard/amd/persimmon/romstage.c
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@ -50,6 +50,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
__writemsr (0xc0010062, 0); __writemsr (0xc0010062, 0);
if (boot_cpu())
{
u8 reg8;
// SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register
outb(0x24, 0xCD6);
reg8 = inb(0xCD7);
reg8 |= 1;
reg8 &= ~(1 << 1);
outb(reg8, 0xCD7);
// program SB800 MiscCntrl
*(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
*(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
}
// early enable of PrefetchEnSPIFromHost // early enable of PrefetchEnSPIFromHost
if (boot_cpu()) if (boot_cpu())
{ {
@ -78,17 +93,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
} }
//reg8 = pmio_read(0x24);
outb(0x24, 0xCD6);
reg8 = inb(0xCD7);
reg8 |= 1;
reg8 &= ~(1 << 1);
//pmio_write(0x24, reg8);
outb(0x24, 0xCD6);
outb(reg8, 0xCD7);
*(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
*(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
post_code(0x34); post_code(0x34);