diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 0b87f2d08e..6203916088 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -326,6 +326,8 @@ struct soc_intel_skylake_config {
 	/* PL2 Override value in Watts */
 	u32 tdp_pl2_override;
 	u8 PmTimerDisabled;
+	/* Intel Speed Shift Technology */
+	u8 speed_shift_enable;
 };
 
 typedef struct soc_intel_skylake_config config_t;
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 2fa858257d..327bee90c3 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -207,6 +207,32 @@ static void configure_thermal_target(void)
 	}
 }
 
+static void configure_isst(void)
+{
+	device_t dev = SA_DEV_ROOT;
+	config_t *conf = dev->chip_info;
+	msr_t msr;
+
+	if (conf->speed_shift_enable) {
+		/*
+		* Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
+		  is supported or not. Coreboot needs to configure MSR 0x1AA
+		  which is then reflected in the CPUID register.
+		*/
+		msr = rdmsr(MSR_MISC_PWR_MGMT);
+		msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */
+		msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */
+		msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */
+		wrmsr(MSR_MISC_PWR_MGMT, msr);
+	} else {
+		msr = rdmsr(MSR_MISC_PWR_MGMT);
+		msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */
+		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */
+		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */
+		wrmsr(MSR_MISC_PWR_MGMT, msr);
+	}
+}
+
 static void configure_misc(void)
 {
 	msr_t msr;
@@ -335,6 +361,9 @@ static void cpu_core_init(device_t cpu)
 	/* Configure Enhanced SpeedStep and Thermal Sensors */
 	configure_misc();
 
+	/* Configure Intel Speed Shift */
+	configure_isst();
+
 	/* Thermal throttle activation offset */
 	configure_thermal_target();
 
diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h
index db154b788f..4d295e186f 100644
--- a/src/soc/intel/skylake/include/soc/msr.h
+++ b/src/soc/intel/skylake/include/soc/msr.h
@@ -36,6 +36,9 @@
 #define IA32_MISC_ENABLE		0x1a0
 #define MSR_MISC_PWR_MGMT		0x1aa
 #define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
+#define  MISC_PWR_MGMT_ISST_EN	(1 << 6)
+#define  MISC_PWR_MGMT_ISST_EN_INT	(1 << 7)
+#define  MISC_PWR_MGMT_ISST_EN_EPP	(1 << 12)
 #define MSR_TURBO_RATIO_LIMIT		0x1ad
 #define MSR_TEMPERATURE_TARGET		0x1a2
 #define IA32_PERF_CTL			0x199