mb/google/hatch/variants/helios: DPTF solution update
Modify DPTF parameters. BUG=b:131272830 BRANCH=firmware-hatch-12672.B TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I93930525edf4c5efb6b73bdfc8f16950754f7c9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/37272 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -18,16 +18,16 @@
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#define DPTF_TSR0_SENSOR_ID 0
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#define DPTF_TSR0_SENSOR_NAME "Battery Charger"
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#define DPTF_TSR0_PASSIVE 50
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#define DPTF_TSR0_PASSIVE 59
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#define DPTF_TSR0_CRITICAL 80
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#define DPTF_TSR1_SENSOR_ID 1
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#define DPTF_TSR1_SENSOR_NAME "5V Regulator"
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#define DPTF_TSR1_PASSIVE 0
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#define DPTF_TSR1_CRITICAL 70
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#define DPTF_TSR1_ACTIVE_AC0 43
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#define DPTF_TSR1_ACTIVE_AC1 40
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#define DPTF_TSR1_ACTIVE_AC2 38
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#define DPTF_TSR1_ACTIVE_AC0 42
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#define DPTF_TSR1_ACTIVE_AC1 41
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#define DPTF_TSR1_ACTIVE_AC2 39
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#define DPTF_TSR2_SENSOR_ID 2
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#define DPTF_TSR2_SENSOR_NAME "Ambient"
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@ -36,14 +36,8 @@
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#define DPTF_TSR3_SENSOR_ID 3
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#define DPTF_TSR3_SENSOR_NAME "CPU"
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#define DPTF_TSR3_PASSIVE 90
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#define DPTF_TSR3_CRITICAL 105
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#define DPTF_TSR3_ACTIVE_AC0 87
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#define DPTF_TSR3_ACTIVE_AC1 85
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#define DPTF_TSR3_ACTIVE_AC2 83
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#define DPTF_TSR3_ACTIVE_AC3 80
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#define DPTF_TSR3_ACTIVE_AC4 78
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#define DPTF_TSR3_ACTIVE_AC5 75
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#define DPTF_TSR3_PASSIVE 44
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#define DPTF_TSR3_CRITICAL 90
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#define DPTF_ENABLE_CHARGER
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#define DPTF_ENABLE_FAN_CONTROL
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@ -91,7 +85,7 @@ Name (DART, Package () {
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 100, 80, 60, 0, 0, 0, 0,
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 70, 50, 0, 0, 0, 0,
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0, 0, 0
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},
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Package () {
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@ -99,7 +93,7 @@ Name (DART, Package () {
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 90, 69, 56, 46, 36, 30, 0,
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0
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}
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})
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