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soc/intel/tigerlake: Add display related UPD configs for Jasper Lake 

TEST=Build dedede board

Change-Id: I942a7036bf627b3d8262756e5e2026dcb0949dd5
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39131
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra 2020-02-26 20:16:55 +05:30 committed by Subrata Banik
parent dba6c4cfc0
commit b7fb24677c
1 changed files with 7 additions and 0 deletions
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7
src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
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@ -87,6 +87,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
/* Display */
m_cfg->DdiPortAConfig = config->DdiPortAConfig;
m_cfg->DdiPortBHpd = config->DdiPortBHpd;
m_cfg->DdiPortCHpd = config->DdiPortCHpd;
m_cfg->DdiPortBDdc = config->DdiPortBDdc;
m_cfg->DdiPortCDdc = config->DdiPortCDdc;
/* Audio */
m_cfg->PchHdaEnable = pcidev_path_on_root(PCH_DEVFN_HDA) ? dev->enabled : 0;