mb/asrock/g41c-gs: Add g41m-gs variant

This board is quite similar to the other ones in this dir an can be
supported with little code changes.

TODO what works:
* DDR2 dual channel PC2-6400;
* SATA;
* USB;
* Ethernet;
* Audio;
* Native graphic init;
* SuperIO Sensors;
* Reboot, poweroff, S3 resume;
* Flashrom (vendor and coreboot);

TODO how tested:
Tests were run with SeaBIOS and Debian stretch, using Linux 4.9.65.

Change-Id: I6844efacaae109cf1e0894201852fddd8043a706
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/mainboard/asrock/g41c-gs/Kconfig

@@ -14,7 +14,7 @@
 # GNU General Public License for more details.
 #
 
-if BOARD_ASROCK_G41C_GS_R2_0 || BOARD_ASROCK_G41C_GS
+if BOARD_ASROCK_G41C_GS_R2_0 || BOARD_ASROCK_G41C_GS || BOARD_ASROCK_G41M_GS
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
@@ -23,7 +23,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select NORTHBRIDGE_INTEL_X4X
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SUPERIO_NUVOTON_NCT6776 if BOARD_ASROCK_G41C_GS_R2_0
-	select SUPERIO_WINBOND_W83627DHG if BOARD_ASROCK_G41C_GS
+	select SUPERIO_WINBOND_W83627DHG if BOARD_ASROCK_G41C_GS \
+		|| BOARD_ASROCK_G41M_GS
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_1024
 	select PCIEXP_ASPM
@@ -44,11 +45,13 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "G41C-GS R2.0" if BOARD_ASROCK_G41C_GS_R2_0
 	default "G41C-GS" if BOARD_ASROCK_G41C_GS
+	default "G41M-GS" if BOARD_ASROCK_G41M_GS
 
 config DEVICETREE
 	string
 	default "variants/g41c-gs-r2/devicetree.cb" if BOARD_ASROCK_G41C_GS_R2_0
 	default "variants/g41c-gs/devicetree.cb" if BOARD_ASROCK_G41C_GS
+	default "variants/g41m-gs/devicetree.cb" if BOARD_ASROCK_G41M_GS
 
 config MAX_CPUS
 	int

src/mainboard/asrock/g41c-gs/Kconfig.name

@@ -3,3 +3,6 @@ config BOARD_ASROCK_G41C_GS_R2_0
 
 config BOARD_ASROCK_G41C_GS
 	bool "G41C-GS / G41C-S"
+
+config BOARD_ASROCK_G41M_GS
+	bool "G41M-GS"

src/mainboard/asrock/g41c-gs/gpio.c

@@ -45,14 +45,22 @@ static const struct pch_gpio_set1 pch_gpio_set1_direction = {
 	.gpio10 = GPIO_DIR_OUTPUT,
 	.gpio12 = GPIO_DIR_INPUT,
 	.gpio13 = GPIO_DIR_INPUT,
+#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS)
+	.gpio14 = GPIO_DIR_OUTPUT,
+#else
 	.gpio14 = GPIO_DIR_INPUT,
+#endif
 	.gpio15 = GPIO_DIR_OUTPUT,
 	.gpio16 = GPIO_DIR_OUTPUT,
 	.gpio18 = GPIO_DIR_OUTPUT,
 	.gpio20 = GPIO_DIR_OUTPUT,
 	.gpio24 = GPIO_DIR_OUTPUT,
 	.gpio25 = GPIO_DIR_OUTPUT,
+#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS)
+	.gpio26 = GPIO_DIR_OUTPUT,
+#else
 	.gpio26 = GPIO_DIR_INPUT,
+#endif
 	.gpio27 = GPIO_DIR_OUTPUT,
 	.gpio28 = GPIO_DIR_INPUT,
 };
@@ -68,15 +76,21 @@ static const struct pch_gpio_set1 pch_gpio_set1_level = {
 	.gpio25 = GPIO_LEVEL_LOW,
 	.gpio27 = GPIO_LEVEL_LOW,
 };
-#else /* BOARD_ASROCK_G41C_GS */
+#else /* BOARD_ASROCK_G41C_GS, BOARD_ASROCK_G41M_GS*/
 static const struct pch_gpio_set1 pch_gpio_set1_level = {
 	.gpio10 = GPIO_LEVEL_LOW,
+#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS)
+	.gpio14 = GPIO_LEVEL_HIGH,
+#endif
 	.gpio15 = GPIO_LEVEL_LOW,
 	.gpio16 = GPIO_LEVEL_HIGH,
 	.gpio18 = GPIO_LEVEL_LOW,
 	.gpio20 = GPIO_LEVEL_HIGH,
 	.gpio24 = GPIO_LEVEL_HIGH,
 	.gpio25 = GPIO_LEVEL_LOW,
+#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS)
+	.gpio26 = GPIO_LEVEL_LOW,
+#endif
 	.gpio27 = GPIO_LEVEL_LOW,
 };
 #endif
@@ -84,6 +98,9 @@ static const struct pch_gpio_set1 pch_gpio_set1_level = {
 static const struct pch_gpio_set1 pch_gpio_set1_invert = {
 	.gpio0 = GPIO_INVERT,
 	.gpio6 = GPIO_INVERT,
+#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS)
+	.gpio8 = GPIO_INVERT,
+#endif
 	.gpio12 = GPIO_INVERT,
 	.gpio13 = GPIO_INVERT,
 };

src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb

@@ -0,0 +1,135 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/x4x		# Northbridge
+	device cpu_cluster 0 on		# APIC cluster
+		chip cpu/intel/socket_LGA775
+			device lapic 0 on end
+		end
+		chip cpu/intel/model_1067x		# CPU
+			device lapic 0xACAC off end
+		end
+	end
+	device domain 0 on		# PCI domain
+		subsystemid 0x1458 0x5000 inherit
+		device pci 0.0 on			# Host Bridge
+			subsystemid 0x1849 0x2e30
+		end
+		device pci 1.0 on end			# PEG
+
+		device pci 2.0 on			# Integrated graphics controller
+			subsystemid 0x1849 0x2e32
+		end
+		device pci 3.0 off end		# ME
+		device pci 3.1 off end		# ME
+		chip southbridge/intel/i82801gx	# Southbridge
+			register "pirqa_routing" = "0x0b"
+			register "pirqb_routing" = "0x0b"
+			register "pirqc_routing" = "0x0b"
+			register "pirqd_routing" = "0x0b"
+			register "pirqe_routing" = "0x80"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x80"
+			register "pirqh_routing" = "0x0b"
+
+			register "ide_enable_primary" = "0x1"
+			register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
+			register "sata_ports_implemented" = "0x3"
+			register "gpe0_en" = "0x440"
+
+			device pci 1b.0 on		# Audio
+				subsystemid 0x1849 0x3662
+			end
+			device pci 1c.0 on end		# PCIe 1
+			device pci 1c.1 on end		# PCIe 2
+			device pci 1c.2 off end		# PCIe 3
+			device pci 1c.3 off end		# PCIe 4
+			device pci 1d.0 on		# USB
+				subsystemid 0x1849 0x27c8
+			end
+			device pci 1d.1 on		# USB
+				subsystemid 0x1849 0x27c9
+			end
+			device pci 1d.2 on		# USB
+				subsystemid 0x1849 0x27ca
+			end
+			device pci 1d.3 on		# USB
+				subsystemid 0x1849 0x27cb
+			end
+			device pci 1d.7 on		# USB
+				subsystemid 0x1849 0x27cc
+			end
+			device pci 1e.0 on end		# PCI bridge
+			device pci 1f.0 on		# ISA bridge
+				subsystemid 0x1849 0x27b8
+					chip superio/winbond/w83627dhg
+					device pnp 2e.0 off end		# Floppy
+					device pnp 2e.1 on		# Parallel port
+						# global
+						irq 0x28 = 0x70
+						irq 0x2c = 0xd2
+						# parallel port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+						drq 0x74 = 3
+					end
+					device pnp 2e.2 on		# COM1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 off end		# COM2
+					device pnp 2e.5 on		# Keyboard & MOUSE
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 0x0C
+					end
+					device pnp 2e.6 off end		# SPI
+					device pnp 2e.7 off end		# GPIO6
+					device pnp 2e.8 off end		# WDT0#, PLED
+					device pnp 2e.9 on end 		# GPIO2
+					device pnp 2e.109 on	# GPIO3
+						irq 0xfe = 0x07
+					end
+					device pnp 2e.209 on		# GPIO4
+						irq 0xf4 = 0x73
+					end
+					device pnp 2e.309 off end	# GPIO5
+					device pnp 2e.a on		# ACPI
+						irq 0xe4 = 0x10 # Power dram during s3
+					end
+					device pnp 2e.b on		# HWM, front pannel LED
+						io 0x60 = 0x290
+						irq 0x70 = 0
+					end
+					device pnp 2e.c off end		# PECI, SST
+				end
+			end
+			device pci 1f.1 on		# PATA/IDE
+				subsystemid 0x1849 0x27df
+			end
+			device pci 1f.2 on		# SATA
+				subsystemid 0x1849 0x27c0
+			end
+			device pci 1f.3 on		# SMbus
+				subsystemid 0x1849 0x27da
+			end
+			device pci 1f.4 off end
+			device pci 1f.5 off end
+			device pci 1f.6 off end
+		end
+	end
+end