soc/intel/meteorlake: Hook up UPD PchHdaSdiEnable

Hook the PchHdaSdiEnable UPD so that mainboard can change the
settings via devicetree. PchHdaSdiEnable UPD enable HDA SDI lanes.

BUG=b:273962021
TEST=Verified the settings on google/rex using debug FSP logs.

Change-Id: I43f1e59d28fc07218f8e25266f8ce3bdcf3f6e5c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75529
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>

src/soc/intel/meteorlake/chip.h

@@ -19,6 +19,7 @@
 #include <stdint.h>
 
 #define MAX_SAGV_POINTS 4
+#define MAX_HD_AUDIO_SDI_LINKS 2
 
 /* Types of different SKUs */
 enum soc_intel_meteorlake_power_limits {
@@ -192,6 +193,8 @@ struct soc_intel_meteorlake_config {
 	/* Audio related */
 	uint8_t pch_hda_dsp_enable;
 
+	bool pch_hda_sdi_enable[MAX_HD_AUDIO_SDI_LINKS];
+
 	/* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */
 	enum {
 		HDA_TMODE_2T = 0,

src/soc/intel/meteorlake/romstage/fsp_params.c

@@ -223,6 +223,10 @@ static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode;
 	m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency;
 	m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable;
+
+	for (int i = 0; i < MAX_HD_AUDIO_SDI_LINKS; i++)
+		m_cfg->PchHdaSdiEnable[i] = config->pch_hda_sdi_enable[i];
+
 	/*
 	 * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to
 	 * configure GPIO pads for audio. Mainboard is expected to perform all GPIO