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intel/skylake: Select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT 

This allows the board to save the recovery request in case of unexpected
reboots caused by FSP.

With recovery module in vboot handling the saving of recovery reason
across reboots, there is no need to have special fsp reset handling
under soc.

BUG=chrome-os-partner:55431

Change-Id: I0b7ce14868a322072d3e60c1dae43f211b43fdbf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15804
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2016-07-22 09:20:56 -07:00
parent 7c7b291e55
commit b8257df83b
3 changed files with 1 additions and 65 deletions
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1
src/soc/intel/skylake/Kconfig
View File

@ -58,6 +58,7 @@ config CHROMEOS
select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC
select VBOOT_EC_SLOW_UPDATE
select VBOOT_OPROM_MATTERS
select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
select VIRTUAL_DEV_SWITCH
config BOOTBLOCK_CPU_INIT

1
src/soc/intel/skylake/Makefile.inc
View File

@ -38,7 +38,6 @@ ramstage-y += dsp.c
ramstage-y += elog.c
ramstage-y += finalize.c
ramstage-y += flash_controller.c
ramstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += fsp_reset.c
ramstage-y += gpio.c
ramstage-y += i2c.c
ramstage-y += igd.c

64
src/soc/intel/skylake/fsp_reset.c
View File

@ -1,64 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <bootstate.h>
#include <vendorcode/google/chromeos/vboot_common.h>
static int is_recovery; /* flag to identify recovery mode */
/*
* coreboot used to clear recovery status towards romstage end after FSP
* memory init. Later inside FSP silicon init due to HSIO CRC mismatch
* or other silicon related programming may request for an additional
* reset. Thus on the next boot the system resumed in normal mode rather than
* recovery because it lost its original state due to FSP silicon init reset.
* Hence it needs an addition reset to get into old state and continue
* booting into recovery mode. This function will set recovery reason
* during Silicon init, in case of recovery mode booting,
* so, system will not lose its original context.
*/
static void set_recovery_request(void *unused)
{
is_recovery = recovery_mode_enabled();
/*
* Set recovery flag during Recovery Mode Silicon Init
* & store recovery request into VBNV
*/
if (is_recovery) {
int reason = vboot_handoff_get_recovery_reason();
set_recovery_mode_into_vbnv(reason);
}
}
static void clear_recovery_request(void *unused)
{
/*
* Done with Silicon Init, it's safe to clear
* reset request now with assumption that no reset occurs hereafter
* so we will not miss original data.
*/
if (is_recovery)
set_recovery_mode_into_vbnv(0);
}
/*
* On Recovery Path Set Recovery Request during early RAMSTAGE
* before initiated Silicon Init
*/
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, set_recovery_request, NULL);
/*
* On Recovery Path Clear Recovery Request during early RAMSTAGE
* end of Silicon Init
*/
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, clear_recovery_request, NULL);