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src: Never set ISA Enable on PCI bridges

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Looks like no one really knows what this bit would be useful for, nor
when it would need to be set. Especially if coreboot is setting it even
on PCI *Express* bridges. Digging through git history, nearly all
instances of setting it on PCIe bridges comes from i82801gx, for which
no reason was given as to why this would be needed. The other instances
in Intel code seem to have been, unsurprisingly, copy-pasted.

Drop all uses of this definition and rename it to avoid confusion. The
negation in the name could trick people into setting this bit again.

Tested on Asrock B85M Pro4, no visible difference.

Change-Id: Ifaff29561769c111fb7897e95dbea842faec5df4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Angel Pons 2020-07-23 23:32:46 +02:00
parent e5ef197726
commit b82b4314ad
9 changed files with 6 additions and 14 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/device/cardbus_device.c
View file

@ -119,7 +119,6 @@ void cardbus_enable_resources(struct device *dev)
ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
ctrl |= (dev->link_list->bridge_ctrl & (
PCI_BRIDGE_CTL_NO_ISA |
PCI_BRIDGE_CTL_VGA |
PCI_BRIDGE_CTL_MASTER_ABORT |
PCI_BRIDGE_CTL_BUS_RESET));

2
src/include/device/pci_def.h
View file

@ -136,7 +136,7 @@
/* Enable parity detection on secondary interface */
#define PCI_BRIDGE_CTL_PARITY 0x01
#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
#define PCI_BRIDGE_CTL_ISA 0x04 /* Disable bridging of ISA ports */
#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
#define PCI_BRIDGE_CTL_VGA16 0x10 /* Enable 16-bit i/o port decoding */
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */

1
src/soc/intel/broadwell/pcie.c
View file

@ -587,7 +587,6 @@ static void pch_pcie_init(struct device *dev)
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
reg16 &= ~PCI_BRIDGE_CTL_PARITY;
reg16 |= PCI_BRIDGE_CTL_NO_ISA;
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Clear errors in status registers */

5
src/soc/intel/common/block/pcie/pcie.c
View file

@ -24,9 +24,8 @@ static void pch_pcie_init(struct device *dev)
/* Set Cache Line Size to 0x10 */
pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE);
/* disable parity error response, enable ISA */
pci_update_config16(dev, PCI_BRIDGE_CONTROL,
~PCI_BRIDGE_CTL_PARITY, PCI_BRIDGE_CTL_NO_ISA);
/* disable parity error response */
pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY);
if (CONFIG(PCIE_DEBUG_INFO)) {
printk(BIOS_SPEW, " MBL = 0x%08x\n",

3
src/southbridge/intel/bd82x6x/pcie.c
View file

@ -216,8 +216,7 @@ static void pci_init(struct device *dev)
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
pci_update_config16(dev, PCI_BRIDGE_CONTROL,
~PCI_BRIDGE_CTL_PARITY, PCI_BRIDGE_CTL_NO_ISA);
pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY);
/* Clear errors in status registers. FIXME: Do something? */
reg16 = pci_read_config16(dev, 0x06);

1
src/southbridge/intel/i82801gx/pcie.c
View file

@ -54,7 +54,6 @@ static void pci_init(struct device *dev)
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
reg16 &= ~PCI_BRIDGE_CTL_PARITY;
reg16 |= PCI_BRIDGE_CTL_NO_ISA;
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Enable IO xAPIC on this PCIe port */

3
src/southbridge/intel/i82801ix/pcie.c
View file

@ -23,8 +23,7 @@ static void pci_init(struct device *dev)
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY,
PCI_BRIDGE_CTL_NO_ISA);
pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY);
/* Enable IO xAPIC on this PCIe port */
pci_or_config32(dev, 0xd8, 1 << 7);

3
src/southbridge/intel/i82801jx/pcie.c
View file

@ -23,8 +23,7 @@ static void pci_init(struct device *dev)
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY,
PCI_BRIDGE_CTL_NO_ISA);
pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY);
/* Enable IO xAPIC on this PCIe port */
pci_or_config32(dev, 0xd8, 1 << 7);

1
src/southbridge/intel/lynxpoint/pcie.c
View file

@ -667,7 +667,6 @@ static void pci_init(struct device *dev)
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
reg16 &= ~PCI_BRIDGE_CTL_PARITY;
reg16 |= PCI_BRIDGE_CTL_NO_ISA;
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Clear errors in status registers */