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soc/amd/picasso: remove broken and unused legacy UART support 

The UARTs in the Picasso SoC are memory mapped, but there is also some
hardware support that isn't used by any board to make the UARTs behave
like the ones found on legacy x86 machines from the 90s.

In the MMIO mode the MMIO address of the UART controller is passed to
the OS via ACPI. The OS expects the base clock of the UART controller to
be 48MHz (see the cz_uart_desc struct in drivers/acpi/acpi_apd.c and
drivers/tty/serial/8250/8250_dw.c in the Linux kernel) in this case. It
is also possible to enable additional decodes from four 8 byte legacy
I/O locations used for serial ports to the different UART controllers,
which doesn't disable the MMIO access though. The legacy I/O-mapped
serial ports are usually expected to have a base clock of 16*115200Hz
which the hardware can also provide to the UART's baud rate generator.
So there are two possible valid configurations to use the UARTs; either
MMIO access in combination with a 48MHz base clock or the legacy I/O
decode with a ~1.8MHz base clock.

The existing code unconditionally generates ACPI objects for all enabled
UARTs, so those shouldn't be put into legacy mode and switching the base
clock to ~1.8MHz was only done in the case that the UART was used as
coreboot console UART which still used the MMIO access, but the lower
base clock. Since no board even selects this option and it's rather
invasive to properly implement this feature, just drop the corresponding
broken code.

TEST=SoC UART console still works on Mandolin.

Change-Id: I26fa8fdfc781b583ba56ac4dbcbbfb6100e84852
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49371
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2021-01-13 01:24:38 +01:00
parent c2d0112200
commit b82cafad93
4 changed files with 1 additions and 99 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
src/soc/amd/common/block/uart/Kconfig
View File

@ -21,31 +21,6 @@ config AMD_SOC_CONSOLE_UART
2: 0xfedc3000
3: 0xfedcf000
choice
prompt "UART Frequency"
depends on AMD_SOC_CONSOLE_UART
default AMD_SOC_UART_48MZ
config AMD_SOC_UART_48MZ
bool "48 MHz clock"
help
Select this option for the most compatibility.
config AMD_SOC_UART_1_8MZ
bool "1.8432 MHz clock"
help
Select this option if an old payload or Linux ttyS0 arguments require
a 1.8432 MHz clock source for the UART.
endchoice
config AMD_SOC_UART_LEGACY
bool "Decode legacy I/O range"
help
Assign I/O 3F8, 2F8, etc. to an integrated AMD SoC UART. A UART
accessed with I/O does not allow all the features of MMIO. The MMIO
decode is still present when this option is used.
config CONSOLE_UART_BASE_ADDRESS
depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART
hex

2
src/soc/amd/common/block/uart/uart_console.c
View File

@ -15,5 +15,5 @@ uintptr_t uart_platform_base(unsigned int idx)
unsigned int uart_platform_refclk(void)
{
return CONFIG(AMD_SOC_UART_48MZ) ? 48000000 : 115200 * 16;
return 48000000;
}

16
src/soc/amd/picasso/include/soc/southbridge.h
View File

@ -13,14 +13,6 @@
* - fixed addresses offset from 0xfed80000
*/
/* SMBus controller registers: 0xfed80000 or D14F0 */
#define SMB_UART_CONFIG 0xfc
#define SMB_UART3_1_8M BIT(31) /* defaults are 0 = 48MHz */
#define SMB_UART2_1_8M BIT(30)
#define SMB_UART1_1_8M BIT(29)
#define SMB_UART0_1_8M BIT(28)
#define SMB_UART_1_8M_SHIFT 28
/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */
#define PM_PCI_CTRL 0x08
#define FORCE_SLPSTATE_RETRY BIT(25)
@ -144,13 +136,6 @@
#define FCH_AOAC_DEV_ESPI 27
#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
#define FCH_LEGACY_UART_MAP_SHIFT 8
#define FCH_LEGACY_UART_MAP_SIZE 2
#define FCH_LEGACY_UART_MAP_MASK 0x3
#define FCH_LEGACY_UART_RANGE_2E8 0
#define FCH_LEGACY_UART_RANGE_2F8 1
#define FCH_LEGACY_UART_RANGE_3E8 2
#define FCH_LEGACY_UART_RANGE_3F8 3
#define PM1_LIMIT 16
#define GPE0_LIMIT 28
@ -196,7 +181,6 @@ void southbridge_final(void *chip_info);
void southbridge_init(void *chip_info);
void fch_pre_init(void);
void fch_early_init(void);
void set_uart_legacy_config(unsigned int uart_idx, unsigned int range_idx);
/* Initialize all the i2c buses that are marked with early init. */
void i2c_soc_early_init(void);

57
src/soc/amd/picasso/uart.c
View File

@ -5,7 +5,6 @@
#include <commonlib/helpers.h>
#include <device/mmio.h>
#include <amdblocks/gpio_banks.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/aoac.h>
#include <soc/southbridge.h>
#include <soc/gpio.h>
@ -42,71 +41,17 @@ uintptr_t get_uart_base(unsigned int idx)
return uart_info[idx].base;
}
static bool get_uart_idx(uintptr_t base, unsigned int *idx)
{
for (unsigned int i = 0; i < ARRAY_SIZE(uart_info); i++) {
if (base == uart_info[i].base) {
*idx = i;
return true;
}
}
return false;
}
void clear_uart_legacy_config(void)
{
write16((void *)FCH_LEGACY_UART_DECODE, 0);
}
void set_uart_legacy_config(unsigned int uart_idx, unsigned int range_idx)
{
uint16_t uart_legacy_decode;
uint8_t uart_map_offset;
if (uart_idx >= ARRAY_SIZE(uart_info) || range_idx >= ARRAY_SIZE(uart_info))
return;
uart_legacy_decode = read16((void *)FCH_LEGACY_UART_DECODE);
/* Map uart_idx to io range_idx */
uart_map_offset = range_idx * FCH_LEGACY_UART_MAP_SIZE + FCH_LEGACY_UART_MAP_SHIFT;
uart_legacy_decode &= ~(FCH_LEGACY_UART_MAP_MASK << uart_map_offset);
uart_legacy_decode |= uart_idx << uart_map_offset;
/* Enable io range */
uart_legacy_decode |= 1 << range_idx;
write16((void *)FCH_LEGACY_UART_DECODE, uart_legacy_decode);
}
static void enable_uart_legacy_decode(uintptr_t base)
{
unsigned int idx;
const uint8_t range_idx[ARRAY_SIZE(uart_info)] = {
FCH_LEGACY_UART_RANGE_3F8,
FCH_LEGACY_UART_RANGE_2F8,
FCH_LEGACY_UART_RANGE_3E8,
FCH_LEGACY_UART_RANGE_2E8,
};
if (get_uart_idx(base, &idx)) {
set_uart_legacy_config(idx, range_idx[idx]);
}
}
void set_uart_config(unsigned int idx)
{
uint32_t uart_ctrl;
if (idx >= ARRAY_SIZE(uart_info))
return;
program_gpios(uart_info[idx].mux, 2);
if (CONFIG(AMD_SOC_UART_1_8MZ)) {
uart_ctrl = sm_pci_read32(SMB_UART_CONFIG);
uart_ctrl |= 1 << (SMB_UART_1_8M_SHIFT + idx);
sm_pci_write32(SMB_UART_CONFIG, uart_ctrl);
}
}
static const char *uart_acpi_name(const struct device *dev)
@ -151,8 +96,6 @@ static void uart_enable(struct device *dev)
if (dev->enabled) {
power_on_aoac_device(dev_id);
wait_for_aoac_enabled(dev_id);
if (CONFIG(AMD_SOC_UART_LEGACY))
enable_uart_legacy_decode(dev->path.mmio.addr);
} else {
power_off_aoac_device(dev_id);
}