intel/sandybridge: Use postcar_frame for MTRR setup
Adapt implementation from skylake. Change-Id: Ica3134a2261d3e84c714264cf75557322f9ef5db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17673 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -225,12 +225,29 @@ before_romstage:
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post_code(0x38)
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/* Get number of MTRRs. */
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/* Clear all of the variable MTRRs. */
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popl %ebx
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movl $MTRR_PHYS_BASE(0), %ecx
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clr %eax
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clr %edx
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1:
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testl %ebx, %ebx
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jz 1f
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wrmsr /* Write MTRR base. */
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inc %ecx
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wrmsr /* Write MTRR mask. */
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inc %ecx
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dec %ebx
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jmp 1b
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1:
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/* Get number of MTRRs. */
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popl %ebx
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movl $MTRR_PHYS_BASE(0), %ecx
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2:
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testl %ebx, %ebx
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jz 2f
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/* Low 32 bits of MTRR base. */
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popl %eax
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@ -248,8 +265,9 @@ before_romstage:
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inc %ecx
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dec %ebx
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jmp 1b
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1:
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jmp 2b
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2:
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post_code(0x39)
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/* And enable cache again after setting MTRRs. */
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@ -19,7 +19,7 @@
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#include <arch/cpu.h>
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#include <arch/io.h>
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#include <cbmem.h>
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#include <cpu/cpu.h>
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#include <console/console.h>
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#include <cpu/intel/romstage.h>
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#include <cpu/x86/mtrr.h>
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#include <program_loading.h>
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@ -44,83 +44,41 @@ void *cbmem_top(void)
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return (void *) smm_region_start();
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}
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static inline u32 *stack_push(u32 *stack, u32 value)
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{
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stack = &stack[-1];
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*stack = value;
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return stack;
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}
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#define ROMSTAGE_RAM_STACK_SIZE 0x5000
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/* setup_stack_and_mtrrs() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use. */
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void *setup_stack_and_mtrrs(void)
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{
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int num_mtrrs;
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u32 *slot;
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u32 mtrr_mask_upper;
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u32 top_of_ram;
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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/* Top of stack needs to be aligned to a 4-byte boundary. */
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slot = (void *)romstage_ram_stack_top();
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num_mtrrs = 0;
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/* The upper bits of the MTRR mask need to set according to the number
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* of physical address bits. */
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mtrr_mask_upper = (1 << (cpu_phys_address_size() - 32)) - 1;
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/* The order for each MTRR is value then base with upper 32-bits of
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* each value coming before the lower 32-bits. The reasoning for
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* this ordering is to create a stack layout like the following:
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* +0: Number of MTRRs
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* +4: MTRR base 0 31:0
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* +8: MTRR base 0 63:32
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* +12: MTRR mask 0 31:0
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* +16: MTRR mask 0 63:32
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* +20: MTRR base 1 31:0
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* +24: MTRR base 1 63:32
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* +28: MTRR mask 1 31:0
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* +32: MTRR mask 1 63:32
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*/
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if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
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die("Unable to initialize postcar frame.\n");
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/* Cache the ROM as WP just below 4GiB. */
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slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
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slot = stack_push(slot, 0); /* upper base */
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slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
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num_mtrrs++;
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postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
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MTRR_TYPE_WRPROT);
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
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slot = stack_push(slot, 0); /* upper base */
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slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
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num_mtrrs++;
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postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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top_of_ram = (uint32_t)cbmem_top();
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top_of_ram = (uintptr_t)cbmem_top();
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/* Cache 8MiB below the top of ram. On sandybridge systems the top of
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* ram under 4GiB is the start of the TSEG region. It is required to
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* be 8MiB aligned. Set this area as cacheable so it can be used later
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* for ramstage before setting up the entire RAM as cacheable. */
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slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
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slot = stack_push(slot, 0); /* upper base */
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slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
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num_mtrrs++;
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postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
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/* Cache 8MiB at the top of ram. Top of ram on sandybridge systems
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* is where the TSEG region resides. However, it is not restricted
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* to SMM mode until SMM has been relocated. By setting the region
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* to cacheable it provides faster access when relocating the SMM
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* handler as well as using the TSEG region for other purposes. */
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slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
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slot = stack_push(slot, 0); /* upper base */
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slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
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num_mtrrs++;
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postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
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/* Save the number of MTRRs to setup. Return the stack location
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* pointing to the number of MTRRs. */
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slot = stack_push(slot, num_mtrrs);
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return slot;
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* pointing to the number of MTRRs.
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*/
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return postcar_commit_mtrrs(&pcf);
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}
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