arch/x86: Make X86 stages select ARCH_X86
Also, don't define the default as this results in spurious lines in the .config. TEST: Build all boards with where config.h differed with BUILD_TIMELESS=1 and remained the same Change-Id: Ic77b696f493d7648f317f0ba0a27fdee5212961e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31316 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -13,7 +13,6 @@
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config ARCH_X86
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config ARCH_X86
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bool
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bool
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default n
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select PCI
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select PCI
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select RELOCATABLE_MODULES
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select RELOCATABLE_MODULES
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@ -21,17 +20,16 @@ config ARCH_X86
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config ARCH_BOOTBLOCK_X86_32
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config ARCH_BOOTBLOCK_X86_32
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bool
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bool
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default n
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select ARCH_X86
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select ARCH_X86
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select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK
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select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK
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config ARCH_VERSTAGE_X86_32
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config ARCH_VERSTAGE_X86_32
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bool
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bool
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default n
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select ARCH_X86
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config ARCH_ROMSTAGE_X86_32
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config ARCH_ROMSTAGE_X86_32
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bool
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bool
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default n
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select ARCH_X86
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config ARCH_POSTCAR_X86_32
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config ARCH_POSTCAR_X86_32
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bool
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bool
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@ -39,23 +37,22 @@ config ARCH_POSTCAR_X86_32
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config ARCH_RAMSTAGE_X86_32
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config ARCH_RAMSTAGE_X86_32
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bool
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bool
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default n
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select ARCH_X86
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# stage selectors for x64
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# stage selectors for x64
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config ARCH_BOOTBLOCK_X86_64
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config ARCH_BOOTBLOCK_X86_64
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bool
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bool
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default n
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select ARCH_X86
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select ARCH_X86
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select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK
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select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK
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config ARCH_VERSTAGE_X86_64
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config ARCH_VERSTAGE_X86_64
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bool
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bool
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default n
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select ARCH_X86
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config ARCH_ROMSTAGE_X86_64
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config ARCH_ROMSTAGE_X86_64
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bool
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bool
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default n
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select ARCH_X86
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config ARCH_POSTCAR_X86_64
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config ARCH_POSTCAR_X86_64
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bool
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bool
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@ -63,7 +60,9 @@ config ARCH_POSTCAR_X86_64
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config ARCH_RAMSTAGE_X86_64
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config ARCH_RAMSTAGE_X86_64
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bool
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bool
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default n
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select ARCH_X86
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if ARCH_X86
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config ARCH_X86_64_PGTBL_LOC
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config ARCH_X86_64_PGTBL_LOC
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hex "x86_64 page table location in CBFS"
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hex "x86_64 page table location in CBFS"
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@ -350,3 +349,5 @@ config MAX_PIRQ_LINKS
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also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
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also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
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table specifies links greater than 4, pirq_route_irqs will not
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table specifies links greater than 4, pirq_route_irqs will not
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function properly, unless this variable is correctly set.
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function properly, unless this variable is correctly set.
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endif
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@ -3,7 +3,6 @@ if BOARD_APPLE_MACBOOK11 || BOARD_APPLE_MACBOOK21 || BOARD_APPLE_IMAC52
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select SYSTEM_TYPE_LAPTOP
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select SYSTEM_TYPE_LAPTOP
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select ARCH_X86
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select CPU_INTEL_SOCKET_M
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select CPU_INTEL_SOCKET_M
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select NORTHBRIDGE_INTEL_I945
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select NORTHBRIDGE_INTEL_I945
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select NORTHBRIDGE_INTEL_SUBTYPE_I945GM
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select NORTHBRIDGE_INTEL_SUBTYPE_I945GM
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@ -20,7 +20,6 @@ if BOARD_ASROCK_G41C_GS || BOARD_ASROCK_G41C_GS_R2_0 || \
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA775
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select CPU_INTEL_SOCKET_LGA775
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select NORTHBRIDGE_INTEL_X4X
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select NORTHBRIDGE_INTEL_X4X
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select SOUTHBRIDGE_INTEL_I82801GX
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select SOUTHBRIDGE_INTEL_I82801GX
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@ -17,7 +17,6 @@ if BOARD_ASUS_P5GC_MX
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA775
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select CPU_INTEL_SOCKET_LGA775
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select NORTHBRIDGE_INTEL_I945
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select NORTHBRIDGE_INTEL_I945
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select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
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select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
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@ -18,7 +18,6 @@ if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO || BOARD_ASUS_P5QL_PRO
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA775
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select CPU_INTEL_SOCKET_LGA775
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select NORTHBRIDGE_INTEL_X4X
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select NORTHBRIDGE_INTEL_X4X
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select SOUTHBRIDGE_INTEL_I82801JX
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select SOUTHBRIDGE_INTEL_I82801JX
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@ -18,7 +18,6 @@ if BOARD_ASUS_P5QPL_AM || BOARD_ASUS_P5G41T_M_LX
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA775
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select CPU_INTEL_SOCKET_LGA775
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select NORTHBRIDGE_INTEL_X4X
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select NORTHBRIDGE_INTEL_X4X
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select SOUTHBRIDGE_INTEL_I82801GX
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select SOUTHBRIDGE_INTEL_I82801GX
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@ -17,7 +17,6 @@ if BOARD_ASUS_P8H61_M_PRO
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select ARCH_X86
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select BOARD_ROMSIZE_KB_4096
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select BOARD_ROMSIZE_KB_4096
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_ACPI_TABLES
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@ -18,7 +18,6 @@ if BOARD_FOXCONN_G41S_K || BOARD_FOXCONN_G41M
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA775
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select CPU_INTEL_SOCKET_LGA775
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select NORTHBRIDGE_INTEL_X4X
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select NORTHBRIDGE_INTEL_X4X
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select SOUTHBRIDGE_INTEL_I82801GX
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select SOUTHBRIDGE_INTEL_I82801GX
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@ -17,7 +17,6 @@ if BOARD_GIGABYTE_GA_945GCM_S2L || BOARD_GIGABYTE_GA_945GCM_S2C
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA775
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select CPU_INTEL_SOCKET_LGA775
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select NORTHBRIDGE_INTEL_I945
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select NORTHBRIDGE_INTEL_I945
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select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
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select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
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@ -2,7 +2,6 @@ if BOARD_GIGABYTE_GA_B75M_D3H || BOARD_GIGABYTE_GA_B75M_D3V || BOARD_GIGABYTE_GA
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select ARCH_X86
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select USE_NATIVE_RAMINIT
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select USE_NATIVE_RAMINIT
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select SOUTHBRIDGE_INTEL_C216
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select SOUTHBRIDGE_INTEL_C216
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@ -17,7 +17,6 @@ if BOARD_GIGABYTE_GA_G41M_ES2L
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA775
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select CPU_INTEL_SOCKET_LGA775
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select NORTHBRIDGE_INTEL_X4X
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select NORTHBRIDGE_INTEL_X4X
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select SOUTHBRIDGE_INTEL_I82801GX
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select SOUTHBRIDGE_INTEL_I82801GX
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@ -17,7 +17,6 @@ if BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61MA_D3V
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select ARCH_X86
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select BOARD_ROMSIZE_KB_4096
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select BOARD_ROMSIZE_KB_4096
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_ACPI_TABLES
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA775
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select CPU_INTEL_SOCKET_LGA775
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select NORTHBRIDGE_INTEL_X4X
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select NORTHBRIDGE_INTEL_X4X
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select SOUTHBRIDGE_INTEL_I82801GX
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select SOUTHBRIDGE_INTEL_I82801GX
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@ -18,7 +18,6 @@ if BOARD_INTEL_DG43GT
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA775
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select CPU_INTEL_SOCKET_LGA775
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select NORTHBRIDGE_INTEL_X4X
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select NORTHBRIDGE_INTEL_X4X
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select SOUTHBRIDGE_INTEL_I82801JX
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select SOUTHBRIDGE_INTEL_I82801JX
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA775
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select CPU_INTEL_SOCKET_LGA775
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select NORTHBRIDGE_INTEL_X4X
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select NORTHBRIDGE_INTEL_X4X
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select SOUTHBRIDGE_INTEL_I82801GX
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select SOUTHBRIDGE_INTEL_I82801GX
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@ -2,7 +2,6 @@ if BOARD_MSI_MS7707
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select ARCH_X86
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select USE_NATIVE_RAMINIT
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select USE_NATIVE_RAMINIT
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SOUTHBRIDGE_INTEL_BD82X6X
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@ -2,7 +2,6 @@ if BOARD_SAPPHIRE_PUREPLATINUMH61
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config BOARD_SPECIFIC_OPTIONS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select ARCH_X86
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select USE_NATIVE_RAMINIT
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select USE_NATIVE_RAMINIT
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SOUTHBRIDGE_INTEL_BD82X6X
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