mb/google/fizz: Enable use of override devicetree

This change enables override device tree for Fizz to allow variants to
provide their own overrides and also moves I2C5 realtek node to
fizz/overridetree.cb since it doesn't apply to some variants being
added for Fizz.

Change-Id: Ia1a069fc539b51a22882ef94b55baf5bf7cd302f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
This commit is contained in:
Furquan Shaikh 2018-10-23 08:03:06 -07:00 committed by Patrick Georgi
parent 156a63881f
commit b87ad06d2d
3 changed files with 21 additions and 9 deletions

View File

@ -29,6 +29,10 @@ config DEVICETREE
string
default "variants/baseboard/devicetree.cb"
config OVERRIDE_DEVICETREE
string
default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
select VBOOT_EC_EFS

View File

@ -418,15 +418,7 @@ chip soc/intel/skylake
device pci 16.4 off end # Management Engine Interface 3
device pci 17.0 on end # SATA
device pci 19.0 on end # UART #2
device pci 19.1 on
chip drivers/i2c/generic
register "hid" = ""10EC5663""
register "name" = ""RT53""
register "desc" = ""Realtek RT5663""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"
device i2c 13 on end
end
end # I2C #5
device pci 19.1 on end # I2C #5
device pci 19.2 off end # I2C #4
device pci 1c.0 on end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2

View File

@ -0,0 +1,16 @@
chip soc/intel/skylake
device domain 0 on
device pci 19.1 on
chip drivers/i2c/generic
register "hid" = ""10EC5663""
register "name" = ""RT53""
register "desc" = ""Realtek RT5663""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"
device i2c 13 on end
end
end # I2C #5
end
end