mb/google/fizz: Enable use of override devicetree
This change enables override device tree for Fizz to allow variants to provide their own overrides and also moves I2C5 realtek node to fizz/overridetree.cb since it doesn't apply to some variants being added for Fizz. Change-Id: Ia1a069fc539b51a22882ef94b55baf5bf7cd302f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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@ -29,6 +29,10 @@ config DEVICETREE
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string
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default "variants/baseboard/devicetree.cb"
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config OVERRIDE_DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config VBOOT
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select VBOOT_EC_EFS
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@ -418,15 +418,7 @@ chip soc/intel/skylake
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 on end # SATA
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device pci 19.0 on end # UART #2
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device pci 19.1 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5663""
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register "name" = ""RT53""
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register "desc" = ""Realtek RT5663""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"
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device i2c 13 on end
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end
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end # I2C #5
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device pci 19.1 on end # I2C #5
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device pci 19.2 off end # I2C #4
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device pci 1c.0 on end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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@ -0,0 +1,16 @@
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chip soc/intel/skylake
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device domain 0 on
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device pci 19.1 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5663""
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register "name" = ""RT53""
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register "desc" = ""Realtek RT5663""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"
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device i2c 13 on end
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end
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end # I2C #5
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end
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end
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