sb/intel/common: Make linking pmbase.c conditional

Change-Id: I6a7cd96699dbeb42a53bf1d25db1bcf93e416e0f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33200
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-06-04 13:57:47 +02:00 committed by Nico Huber
parent 63998adf4a
commit b8bda11487
9 changed files with 16 additions and 2 deletions

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@ -30,6 +30,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select HAVE_SMI_HANDLER

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@ -9,6 +9,11 @@ config SOUTHBRIDGE_INTEL_COMMON_RESET
config SOUTHBRIDGE_INTEL_COMMON_PMCLIB
def_bool n
depends on SOUTHBRIDGE_INTEL_COMMON
depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
config SOUTHBRIDGE_INTEL_COMMON_PMBASE
def_bool n
depends on SOUTHBRIDGE_INTEL_COMMON
config SOUTHBRIDGE_INTEL_COMMON_GPIO
def_bool n
@ -36,6 +41,7 @@ config SOUTHBRIDGE_INTEL_COMMON_SMM
def_bool n
select HAVE_POWER_STATE_AFTER_FAILURE
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
bool
@ -78,6 +84,7 @@ config INTEL_CHIPSET_LOCKDOWN
config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
bool
depends on SOUTHBRIDGE_INTEL_COMMON
depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
if SOUTHBRIDGE_INTEL_COMMON_FINALIZE

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@ -27,8 +27,8 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG) += watchdog.c
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y)
all-y += pmbase.c
smm-y += pmbase.c
all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c
smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c
bootblock-$(CONFIG_USBDEBUG) += usb_debug.c
romstage-$(CONFIG_USBDEBUG) += usb_debug.c

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@ -32,6 +32,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_COMMON
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
config EHCI_BAR
hex

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@ -26,6 +26,7 @@ config SOUTHBRIDGE_INTEL_I82801GX
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
select HAVE_INTEL_CHIPSET_LOCKDOWN
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select INTEL_HAS_TOP_SWAP

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@ -20,6 +20,7 @@ config SOUTHBRIDGE_INTEL_I82801IX
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
select IOAPIC
select HAVE_USBDEBUG
select USE_WATCHDOG_ON_BOOT

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@ -21,6 +21,7 @@ config SOUTHBRIDGE_INTEL_I82801JX
select SOUTHBRIDGE_INTEL_COMMON_SPI
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
select IOAPIC
select HAVE_USBDEBUG
select USE_WATCHDOG_ON_BOOT

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@ -34,6 +34,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_COMMON_SPI
select SOUTHBRIDGE_INTEL_COMMON_SMM
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
select HAVE_USBDEBUG_OPTIONS
select COMMON_FADT
select ACPI_SATA_GENERATOR

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@ -27,6 +27,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
select IOAPIC
select HAVE_SMI_HANDLER
select HAVE_USBDEBUG_OPTIONS