flashrom: split flash_enable.c into chipset_enable.c and board_enable.c
This splits up the ROM Write enable code into chipset specific and board specific parts. This of course means that a lot of code is plainly moved about. * Allows for linuxbios name matching and pci-subsystem id matching. The latter uses a double set to properly distuinguish boards despite of some known vendors being lax about it. * Fixes GPIO15 being raised on every VT8235 southbridge, regardless of what that line actually controls; rom on EPIA-M, backlight on mitac 8999 laptop. * Adds flashrom support for Asus A7V400-MX (KM400 + VT8235) * Island aruma was renamed agami aruma, the board specific code now got adjusted. A set of pci-ids was retrieved from source code. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2581 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Luc Verhaegen
Stefan Reinauer
parent
17d667b411
commit
b8c6437811
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@ -20,10 +20,11 @@ LDFLAGS = -lpci -lz -static
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STRIP_ARGS = -s
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endif
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OBJS = flash_enable.o udelay.o jedec.o sst28sf040.o am29f040b.o mx29f002.o \
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sst39sf020.o m29f400bt.o w49f002u.o 82802ab.o msys_doc.o pm49fl004.o \
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sst49lf040.o sst49lfxxxc.o sst_fwhub.o layout.o lbtable.o \
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flashchips.o flash_rom.o sharplhf00l04.o
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OBJS = chipset_enable.o board_enable.o udelay.o jedec.o sst28sf040.o \
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am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o w49f002u.o \
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82802ab.o msys_doc.o pm49fl004.o sst49lf040.o sst49lfxxxc.o \
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sst_fwhub.o layout.o lbtable.o flashchips.o flash_rom.o \
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sharplhf00l04.o
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all: pciutils dep $(PROGRAM)
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@ -0,0 +1,299 @@
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/*
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* flash rom utility: enable flash writes (board specific)
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*
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* Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
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* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2007 Luc Verhaegen <libv@skynet.be>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2
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*
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*/
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/*
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* Contains the board specific flash enables.
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*/
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#include <stdio.h>
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#include <pci/pci.h>
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#include <stdint.h>
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#include <string.h>
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#include "flash.h"
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#include "debug.h"
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/*
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* Match on pci-ids, no report received, just data from the mainboard
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* specific code:
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* main: 0x1022:0x746B, which is the SMBUS controller.
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* card: 0x1022:0x36C0...
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*/
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static int board_agami_aruma(char *name)
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{
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/* Extended function index register, either 0x2e or 0x4e */
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#define EFIR 0x2e
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/* Extended function data register, one plus the index reg. */
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#define EFDR EFIR + 1
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char b;
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/* Disable the flash write protect. The flash write protect is
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* connected to the WinBond w83627hf GPIO 24.
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*/
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outb(0x87, EFIR); /* sequence to unlock extended functions */
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outb(0x87, EFIR);
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outb(0x20, EFIR); /* SIO device ID register */
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b = inb(EFDR);
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printf_debug("\nW83627HF device ID = 0x%x\n",b);
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if (b != 0x52) {
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fprintf(stderr, "\nIncorrect device ID, aborting write protect disable\n");
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return -1;
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}
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outb(0x2b, EFIR); /* GPIO multiplexed pin reg. */
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b = inb(EFDR) | 0x10;
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outb(0x2b, EFIR);
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outb(b, EFDR); /* select GPIO 24 instead of WDTO */
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outb(0x7, EFIR); /* logical device select */
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outb(0x8, EFDR); /* point to device 8, GPIO port 2 */
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outb(0x30, EFIR); /* logic device activation control */
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outb(0x1, EFDR); /* activate */
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outb(0xf0, EFIR); /* GPIO 20-27 I/O selection register */
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b = inb(EFDR) & ~0x10;
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outb(0xf0, EFIR);
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outb(b, EFDR); /* set GPIO 24 as an output */
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outb(0xf1, EFIR); /* GPIO 20-27 data register */
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b = inb(EFDR) | 0x10;
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outb(0xf1, EFIR);
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outb(b, EFDR); /* set GPIO 24 */
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outb(0xaa, EFIR); /* command to exit extended functions */
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return 0;
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}
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/*
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* Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
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*
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* We don't need to do this when using linuxbios, GPIO15 is never lowered there.
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*/
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static int board_via_epia_m(char *name)
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{
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struct pci_dev *dev;
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unsigned int base;
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uint8_t val;
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dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
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if (!dev) {
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fprintf(stderr, "\nERROR: VT8235 ISA Bridge not found.\n");
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return -1;
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}
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/* GPIO12-15 -> output */
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val = pci_read_byte(dev, 0xE4);
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val |= 0x10;
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pci_write_byte(dev, 0xE4, val);
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/* Get Power Management IO address. */
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base = pci_read_word(dev, 0x88) & 0xFF80;
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/* enable GPIO15 which is connected to write protect. */
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val = inb(base + 0x4D);
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val |= 0x80;
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outb(val, base + 0x4D);
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return 0;
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}
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/*
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* Winbond LPC super IO.
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*
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* Raises the ROM MEMW# line.
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*/
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static void w83697_rom_memw_enable(void)
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{
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uint8_t val;
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outb(0x87, 0x2E); /* enable extended functions */
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outb(0x87, 0x2E);
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outb(0x24, 0x2E); /* rom bits live here */
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val = inb(0x2F);
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if (!(val & 0x02)) /* flash rom enabled? */
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outb(val | 0x08, 0x2F); /* enable MEMW# */
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outb(0xAA, 0x2E); /* disable extended functions */
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}
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/*
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* Suited for Asus A7V8X-MX SE and A7V400-MX.
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*
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*/
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static int board_asus_a7v8x_mx(char *name)
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{
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struct pci_dev *dev;
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uint8_t val;
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dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
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if (!dev) {
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fprintf(stderr, "\nERROR: VT8235 ISA Bridge not found.\n");
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return -1;
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}
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/* This bit is marked reserved actually */
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val = pci_read_byte(dev, 0x59);
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val &= 0x7F;
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pci_write_byte(dev, 0x59, val);
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w83697_rom_memw_enable();
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return 0;
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}
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/*
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* We use 2 sets of ids here, you're free to choose which is which. This
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* to provide a very high degree of certainty when matching a board on
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* the basis of Subsystem/card ids. As not every vendor handles
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* subsystem/card ids in a sane manner.
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*
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* Keep the second set nulled if it should be ignored.
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*
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*/
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struct board_pciid_enable {
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/* Any device, but make it sensible, like the isa bridge. */
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uint16_t first_vendor;
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uint16_t first_device;
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uint16_t first_card_vendor;
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uint16_t first_card_device;
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/* Any device, but make it sensible, like
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* the host bridge. May be NULL
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*/
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uint16_t second_vendor;
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uint16_t second_device;
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uint16_t second_card_vendor;
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uint16_t second_card_device;
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/* From linuxbios table */
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char *lb_vendor;
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char *lb_part;
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char *name;
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int (*enable)(char *name);
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};
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struct board_pciid_enable board_pciid_enables[] = {
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{ 0x1022, 0x746B, 0x1022, 0x36C0, 0x0000, 0x0000, 0x0000, 0x0000,
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"AGAMI", "ARUMA", "Agami Aruma", board_agami_aruma },
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{ 0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01,
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NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m },
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{ 0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118,
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NULL, NULL, "Asus A7V8-MX SE", board_asus_a7v8x_mx },
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{ 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL } /* Keep this */
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};
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/*
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* Match boards on linuxbios table gathered vendor and part name.
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* Require main pci-ids to match too as extra safety.
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*
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*/
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static struct board_pciid_enable *
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board_match_linuxbios_name(char *vendor, char *part)
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{
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struct board_pciid_enable *board = board_pciid_enables;
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for (; board->name; board++) {
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if (!board->lb_vendor || strcmp(board->lb_vendor, vendor))
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continue;
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if (!board->lb_part || strcmp(board->lb_part, part))
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continue;
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if (!pci_dev_find(board->first_vendor, board->first_device))
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continue;
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if (board->second_vendor &&
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!pci_dev_find(board->second_vendor, board->second_device))
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continue;
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return board;
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}
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return NULL;
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}
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/*
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* Match boards on pci ids and subsystem ids.
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* Second set of ids can be main only or missing completely.
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*/
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static struct board_pciid_enable *board_match_pci_card_ids(void)
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{
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struct board_pciid_enable *board = board_pciid_enables;
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for (; board->name; board++) {
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if (!board->first_card_vendor || !board->first_card_device)
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continue;
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if (!pci_card_find(board->first_vendor, board->first_device,
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board->first_card_vendor,
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board->first_card_device))
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continue;
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if (board->second_vendor) {
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if (board->second_card_vendor) {
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if (!pci_card_find(board->second_vendor,
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board->second_device,
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board->second_card_vendor,
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board->second_card_device))
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continue;
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} else {
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if (!pci_dev_find(board->second_vendor,
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board->second_device))
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continue;
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}
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}
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return board;
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}
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return NULL;
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}
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/*
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*
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*/
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int board_flash_enable(char *vendor, char *part)
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{
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struct board_pciid_enable *board = NULL;
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int ret = 0;
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if (vendor && part)
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board = board_match_linuxbios_name(vendor, part);
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if (!board)
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board = board_match_pci_card_ids();
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if (board) {
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printf("Found board \"%s\": Enabling flash write... ",
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board->name);
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ret = board->enable(board->name);
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if (ret)
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printf("Failed!\n");
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else
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printf("OK.\n");
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}
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return ret;
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}
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@ -1,8 +1,8 @@
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/*
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* flash rom utility: enable flash writes
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*
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* Copyright (C) 2000-2004 ???
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* Copyright (C) 2005 coresystems GmbH <stepan@openbios.org>
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* Copyright (C) 2000 Silicon Integrated System Corporation
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* Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
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* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or
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@ -14,20 +14,9 @@
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#include <stdio.h>
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#include <pci/pci.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#if defined (__sun) && (defined(__i386) || defined(__amd64))
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#include <strings.h>
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#include <sys/sysi86.h>
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#include <sys/psw.h>
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#include <asm/sunddi.h>
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#endif
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#include "flash.h"
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#include "lbtable.h"
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#include "debug.h"
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// We keep this for the others.
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static struct pci_access *pacc;
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#include "flash.h"
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#include "debug.h"
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static int enable_flash_sis630(struct pci_dev *dev, char *name)
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{
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@ -158,10 +147,13 @@ static int enable_flash_ich_dc(struct pci_dev *dev, char *name)
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return enable_flash_ich(dev, name, 0xdc);
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}
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static int enable_flash_vt823x(struct pci_dev *dev, char *name)
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/*
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*
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*/
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static int
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enable_flash_vt823x(struct pci_dev *dev, char *name)
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{
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uint8_t val;
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int ret = 0;
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/* ROM Write enable */
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val = pci_read_byte(dev, 0x40);
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@ -169,38 +161,12 @@ static int enable_flash_vt823x(struct pci_dev *dev, char *name)
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pci_write_byte(dev, 0x40, val);
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if (pci_read_byte(dev, 0x40) != val) {
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printf("Warning: Failed to enable ROM Write on %s\n", name);
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ret = -1;
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}
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if (dev->device_id == 0x3177) { /* VT8235 */
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if (!iopl(3)) { /* enable full IO access */
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unsigned int base;
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/* GPIO12-15 -> output */
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val = pci_read_byte(dev, 0xE4);
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val |= 0x38;
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pci_write_byte(dev, 0xE4, val);
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/* Get Power Management IO address. */
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base = pci_read_word(dev, 0x88) & 0xFF80;
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/* enable GPIO15 which is connected to write protect. */
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val = inb(base + 0x4d);
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val |= 0xFF;
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outb(val, base + 0x4d);
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val = inb(base + 0x4E);
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val |= 0x0F;
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outb(val, base + 0x4E);
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} else {
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printf("Warning; Failed to disable Write Protect"
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" on %s (iopl failed)\n", name);
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printf("\nWARNING: Failed to enable ROM Write on \"%s\"\n",
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name);
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return -1;
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}
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}
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return ret;
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return 0;
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}
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static int enable_flash_cs5530(struct pci_dev *dev, char *name)
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@ -296,7 +262,6 @@ static int enable_flash_amd8111(struct pci_dev *dev, char *name)
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return 0;
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}
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//By yhlu
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static int enable_flash_ck804(struct pci_dev *dev, char *name)
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{
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/* register 4e.b gets or'ed with one */
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@ -305,7 +270,7 @@ static int enable_flash_ck804(struct pci_dev *dev, char *name)
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* that it is hard to argue that we should quit at this point.
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*/
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//dump_pci_device(dev);
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/* dump_pci_device(dev); */
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old = pci_read_byte(dev, 0x88);
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new = old | 0xc0;
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@ -350,21 +315,21 @@ static int enable_flash_sb400(struct pci_dev *dev, char *name)
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}
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if(!smbusdev) {
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perror("smbus device not found. aborting\n");
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fprintf(stderr, "ERROR: SMBus device not found. aborting\n");
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exit(1);
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}
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// enable some smbus stuff
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/* enable some smbus stuff */
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tmp=pci_read_byte(smbusdev, 0x79);
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tmp|=0x01;
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pci_write_byte(smbusdev, 0x79, tmp);
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// change southbridge
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/* change southbridge */
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tmp=pci_read_byte(dev, 0x48);
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tmp|=0x21;
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pci_write_byte(dev, 0x48, tmp);
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// now become a bit silly.
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/* now become a bit silly. */
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tmp=inb(0xc6f);
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outb(tmp,0xeb);
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outb(tmp, 0xeb);
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@ -376,7 +341,6 @@ static int enable_flash_sb400(struct pci_dev *dev, char *name)
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return 0;
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}
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//By yhlu
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static int enable_flash_mcp55(struct pci_dev *dev, char *name)
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{
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/* register 4e.b gets or'ed with one */
|
||||
|
|
@ -387,17 +351,17 @@ static int enable_flash_mcp55(struct pci_dev *dev, char *name)
|
|||
* that it is hard to argue that we should quit at this point.
|
||||
*/
|
||||
|
||||
//dump_pci_device(dev);
|
||||
/* dump_pci_device(dev); */
|
||||
|
||||
/* Set the 4MB enable bit bit */
|
||||
byte = pci_read_byte(dev, 0x88);
|
||||
byte |= 0xff; //256K
|
||||
byte |= 0xff; /* 256K */
|
||||
pci_write_byte(dev, 0x88, byte);
|
||||
byte = pci_read_byte(dev, 0x8c);
|
||||
byte |= 0xff; //1M
|
||||
byte |= 0xff; /* 1M */
|
||||
pci_write_byte(dev, 0x8c, byte);
|
||||
word = pci_read_word(dev, 0x90);
|
||||
word |= 0x7fff; //15M
|
||||
word |= 0x7fff; /* 15M */
|
||||
pci_write_word(dev, 0x90, word);
|
||||
|
||||
old = pci_read_byte(dev, 0x6d);
|
||||
|
|
@ -451,147 +415,55 @@ static FLASH_ENABLE enables[] = {
|
|||
{0x100b, 0x0510, "SC1100", enable_flash_sc1100},
|
||||
{0x1039, 0x0008, "SIS5595", enable_flash_sis5595},
|
||||
{0x1022, 0x7468, "AMD8111", enable_flash_amd8111},
|
||||
// this fallthrough looks broken.
|
||||
{0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, // LPC
|
||||
{0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, // Pro
|
||||
{0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, // Slave, should not be here, to fix known bug for A01.
|
||||
/* this fallthrough looks broken. */
|
||||
{0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */
|
||||
{0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */
|
||||
{0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, /* Slave, should not be here, to fix known bug for A01. */
|
||||
|
||||
{0x10de, 0x0260, "NVidia MCP51", enable_flash_ck804},
|
||||
{0x10de, 0x0261, "NVidia MCP51", enable_flash_ck804},
|
||||
{0x10de, 0x0262, "NVidia MCP51", enable_flash_ck804},
|
||||
{0x10de, 0x0263, "NVidia MCP51", enable_flash_ck804},
|
||||
|
||||
{0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, // Gigabyte m57sli-s4
|
||||
{0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, // LPC
|
||||
{0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, // LPC
|
||||
{0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, // LPC
|
||||
{0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, // LPC
|
||||
{0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, // LPC
|
||||
{0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, // LPC
|
||||
{0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, // Pro
|
||||
{0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* Gigabyte m57sli-s4 */
|
||||
{0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
||||
{0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
||||
{0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
||||
{0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
||||
{0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
||||
{0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
||||
{0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */
|
||||
|
||||
{0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, // ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80)
|
||||
{0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
|
||||
};
|
||||
|
||||
static int mbenable_island_aruma(void)
|
||||
{
|
||||
#define EFIR 0x2e /* Extended function index register, either 0x2e or 0x4e */
|
||||
#define EFDR EFIR + 1 /* Extended function data register, one plus the index reg. */
|
||||
char b;
|
||||
|
||||
/* Disable the flash write protect. The flash write protect is
|
||||
* connected to the WinBond w83627hf GPIO 24.
|
||||
/*
|
||||
*
|
||||
*/
|
||||
|
||||
printf("Disabling mainboard flash write protection.\n");
|
||||
|
||||
outb(0x87, EFIR); // sequence to unlock extended functions
|
||||
outb(0x87, EFIR);
|
||||
|
||||
outb(0x20, EFIR); // SIO device ID register
|
||||
b = inb(EFDR);
|
||||
printf_debug("W83627HF device ID = 0x%x\n",b);
|
||||
|
||||
if (b != 0x52) {
|
||||
perror("Incorrect device ID, aborting write protect disable\n");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
outb(0x2b, EFIR); // GPIO multiplexed pin reg.
|
||||
b = inb(EFDR) | 0x10;
|
||||
outb(0x2b, EFIR);
|
||||
outb(b, EFDR); // select GPIO 24 instead of WDTO
|
||||
|
||||
outb(0x7, EFIR); // logical device select
|
||||
outb(0x8, EFDR); // point to device 8, GPIO port 2
|
||||
|
||||
outb(0x30, EFIR); // logic device activation control
|
||||
outb(0x1, EFDR); // activate
|
||||
|
||||
outb(0xf0, EFIR); // GPIO 20-27 I/O selection register
|
||||
b = inb(EFDR) & ~0x10;
|
||||
outb(0xf0, EFIR);
|
||||
outb(b, EFDR); // set GPIO 24 as an output
|
||||
|
||||
outb(0xf1, EFIR); // GPIO 20-27 data register
|
||||
b = inb(EFDR) | 0x10;
|
||||
outb(0xf1, EFIR);
|
||||
outb(b, EFDR); // set GPIO 24
|
||||
|
||||
outb(0xaa, EFIR); // command to exit extended functions
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
typedef struct mbenable {
|
||||
char *vendor, *part;
|
||||
int (*doit)(void);
|
||||
} MAINBOARD_ENABLE;
|
||||
|
||||
static MAINBOARD_ENABLE mbenables[] = {
|
||||
{ "ISLAND", "ARUMA", mbenable_island_aruma },
|
||||
};
|
||||
|
||||
int enable_flash_write()
|
||||
int
|
||||
chipset_flash_enable(void)
|
||||
{
|
||||
int i;
|
||||
struct pci_dev *dev = 0;
|
||||
FLASH_ENABLE *enable = 0;
|
||||
|
||||
/* get io privilege access PCI configuration space */
|
||||
#if defined (__sun) && (defined(__i386) || defined(__amd64))
|
||||
if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0){
|
||||
#else
|
||||
if (iopl(3) != 0) {
|
||||
#endif
|
||||
perror("Can not set io privilege");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
|
||||
/* Initialize PCI access */
|
||||
pacc = pci_alloc(); /* Get the pci_access structure */
|
||||
/* Set all options you want -- here we stick with the defaults */
|
||||
pci_init(pacc); /* Initialize the PCI library */
|
||||
pci_scan_bus(pacc); /* We want to get the list of devices */
|
||||
|
||||
|
||||
/* First look whether we have to do something for this
|
||||
* motherboard.
|
||||
*/
|
||||
for (i = 0; i < sizeof(mbenables) / sizeof(mbenables[0]); i++) {
|
||||
if(lb_vendor && !strcmp(mbenables[i].vendor, lb_vendor) &&
|
||||
lb_part && !strcmp(mbenables[i].part, lb_part)) {
|
||||
mbenables[i].doit();
|
||||
break;
|
||||
}
|
||||
}
|
||||
int ret = -2; /* nothing! */
|
||||
int i;
|
||||
|
||||
/* now let's try to find the chipset we have ... */
|
||||
for (i = 0; i < sizeof(enables) / sizeof(enables[0]) && (!dev);
|
||||
i++) {
|
||||
struct pci_filter f;
|
||||
struct pci_dev *z;
|
||||
/* the first param is unused. */
|
||||
pci_filter_init((struct pci_access *) 0, &f);
|
||||
f.vendor = enables[i].vendor;
|
||||
f.device = enables[i].device;
|
||||
for (z = pacc->devices; z; z = z->next)
|
||||
if (pci_filter_match(&f, z)) {
|
||||
enable = &enables[i];
|
||||
dev = z;
|
||||
}
|
||||
for (i = 0; i < sizeof(enables) / sizeof(enables[0]); i++) {
|
||||
dev = pci_dev_find(enables[i].vendor, enables[i].device);
|
||||
if (dev)
|
||||
break;
|
||||
}
|
||||
|
||||
if (!enable) {
|
||||
printf("Warning: Unknown system. Flash detection "
|
||||
"will most likely fail.\n");
|
||||
return 1;
|
||||
if (dev) {
|
||||
printf("Found chipset \"%s\": Enabling flash write... ",
|
||||
enables[i].name);
|
||||
|
||||
ret = enables[i].doit(dev, enables[i].name);
|
||||
if (ret)
|
||||
printf("Failed!\n");
|
||||
else
|
||||
printf("OK.\n");
|
||||
}
|
||||
|
||||
/* now do the deed. */
|
||||
printf("Enabling flash write on %s...", enable->name);
|
||||
if (enable->doit(dev, enable->name) == 0)
|
||||
printf("OK\n");
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* Copyright 2000 Silicon Integrated System Corporation
|
||||
* Copyright 2000 Ronald G. Minnich <rminnich@gmail.com>
|
||||
* Copyright 2005 coresystems GmbH <stepan@coresystems.de>
|
||||
* Copyright 2005-2007 coresystems GmbH <stepan@coresystems.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -128,7 +128,15 @@ extern struct flashchip flashchips[];
|
|||
|
||||
extern void myusec_delay(int time);
|
||||
extern void myusec_calibrate_delay();
|
||||
extern int enable_flash_write(void);
|
||||
|
||||
/* pci handling for board/chipset_enable */
|
||||
extern struct pci_access *pacc; /* For board and chipset_enable */
|
||||
extern struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
|
||||
extern struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
|
||||
uint16_t card_vendor, uint16_t card_device);
|
||||
|
||||
extern int board_flash_enable(char *vendor, char *part); /* board_enable.c */
|
||||
extern int chipset_flash_enable(void); /* chipset_enable.c */
|
||||
|
||||
/* physical memory mapping device */
|
||||
|
||||
|
|
|
|||
|
|
@ -35,6 +35,15 @@
|
|||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
#include <getopt.h>
|
||||
#include <pci/pci.h>
|
||||
|
||||
/* for iopl */
|
||||
#if defined (__sun) && (defined(__i386) || defined(__amd64))
|
||||
#include <strings.h>
|
||||
#include <sys/sysi86.h>
|
||||
#include <sys/psw.h>
|
||||
#include <asm/sunddi.h>
|
||||
#endif
|
||||
|
||||
#include "flash.h"
|
||||
#include "lbtable.h"
|
||||
|
|
@ -42,10 +51,54 @@
|
|||
#include "debug.h"
|
||||
|
||||
char *chip_to_probe = NULL;
|
||||
|
||||
struct pci_access *pacc; /* For board and chipset_enable */
|
||||
int exclude_start_page, exclude_end_page;
|
||||
int force=0, verbose=0;
|
||||
|
||||
/*
|
||||
*
|
||||
*/
|
||||
struct pci_dev *
|
||||
pci_dev_find(uint16_t vendor, uint16_t device)
|
||||
{
|
||||
struct pci_dev *temp;
|
||||
struct pci_filter filter;
|
||||
|
||||
pci_filter_init(NULL, &filter);
|
||||
filter.vendor = vendor;
|
||||
filter.device = device;
|
||||
|
||||
for (temp = pacc->devices; temp; temp = temp->next)
|
||||
if (pci_filter_match(&filter, temp))
|
||||
return temp;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
*
|
||||
*/
|
||||
struct pci_dev *
|
||||
pci_card_find(uint16_t vendor, uint16_t device,
|
||||
uint16_t card_vendor, uint16_t card_device)
|
||||
{
|
||||
struct pci_dev *temp;
|
||||
struct pci_filter filter;
|
||||
|
||||
pci_filter_init(NULL, &filter);
|
||||
filter.vendor = vendor;
|
||||
filter.device = device;
|
||||
|
||||
for (temp = pacc->devices; temp; temp = temp->next)
|
||||
if (pci_filter_match(&filter, temp)) {
|
||||
if ((card_vendor == pci_read_word(temp, 0x2C)) &&
|
||||
(card_device == pci_read_word(temp, 0x2E)))
|
||||
return temp;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
struct flashchip *probe_flash(struct flashchip *flash)
|
||||
{
|
||||
int fd_mem;
|
||||
|
|
@ -72,10 +125,11 @@ struct flashchip *probe_flash(struct flashchip *flash)
|
|||
__FUNCTION__, flash->total_size * 1024,
|
||||
(unsigned long) size);
|
||||
}
|
||||
|
||||
bios = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
|
||||
fd_mem, (off_t) (0xffffffff - size + 1));
|
||||
if (bios == MAP_FAILED) {
|
||||
perror("Error: Can't mmap /dev/mem.");
|
||||
perror("Error: Can't mmap " MEM_DEV ".");
|
||||
exit(1);
|
||||
}
|
||||
flash->virt_addr = bios;
|
||||
|
|
@ -92,7 +146,7 @@ struct flashchip *probe_flash(struct flashchip *flash)
|
|||
bios = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
|
||||
fd_mem, (off_t) (0x9400000));
|
||||
if (bios == MAP_FAILED) {
|
||||
perror("Error: Can't mmap /dev/mem.");
|
||||
perror("Error: Can't mmap " MEM_DEV ".");
|
||||
exit(1);
|
||||
}
|
||||
flash->virt_addr = bios;
|
||||
|
|
@ -281,6 +335,22 @@ int main(int argc, char *argv[])
|
|||
if (optind < argc)
|
||||
filename = argv[optind++];
|
||||
|
||||
/* First get full io access */
|
||||
#if defined (__sun) && (defined(__i386) || defined(__amd64))
|
||||
if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0){
|
||||
#else
|
||||
if (iopl(3) != 0) {
|
||||
#endif
|
||||
fprintf(stderr, "ERROR: iopl failed: \"%s\"\n", strerror(errno));
|
||||
exit(1);
|
||||
}
|
||||
|
||||
/* Initialize PCI access for flash enables */
|
||||
pacc = pci_alloc(); /* Get the pci_access structure */
|
||||
/* Set all options you want -- here we stick with the defaults */
|
||||
pci_init(pacc); /* Initialize the PCI library */
|
||||
pci_scan_bus(pacc); /* We want to get the list of devices */
|
||||
|
||||
printf("Calibrating delay loop... ");
|
||||
myusec_calibrate_delay();
|
||||
printf("ok\n");
|
||||
|
|
@ -293,7 +363,13 @@ int main(int argc, char *argv[])
|
|||
/* try to enable it. Failure IS an option, since not all motherboards
|
||||
* really need this to be done, etc., etc.
|
||||
*/
|
||||
(void) enable_flash_write();
|
||||
ret = chipset_flash_enable();
|
||||
if (ret == -2)
|
||||
printf("WARNING: No chipset found. Flash detection "
|
||||
"will most likely fail.\n");
|
||||
|
||||
board_flash_enable(lb_vendor, lb_part);
|
||||
|
||||
|
||||
if ((flash = probe_flash(flashchips)) == NULL) {
|
||||
printf("No EEPROM/flash device found.\n");
|
||||
|
|
|
|||
Loading…
Reference in New Issue