sb/amd/pi/hudson: Enable use of common GPIO API
The code in soc/amd/common has an implementation of GPIO register space that is compatible with the hardware sb/amd/pi/hudson supports. Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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@ -19,6 +19,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
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select HAVE_CF9_RESET_PREPARE
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select SOC_AMD_COMMON
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select SOC_AMD_COMMON_BLOCK_ACPIMMIO
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select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
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select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
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config EHCI_BAR
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@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOC_GPIO_H
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#define SOC_GPIO_H
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/* <soc/gpio.h> must provide gpio_t. */
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#include <amdblocks/gpio_banks.h>
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#endif /* SOC_GPIO_H */
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@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOC_SMI_H
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#define SOC_SMI_H
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#define SMI_SCI_TRIG 0x08
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#define SMI_SCI_LEVEL 0x0c
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#define SMI_SCI_STATUS 0x10
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#define SMI_SCI_EN 0x14
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#endif /* SOC_SMI_H */
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@ -76,7 +76,7 @@ export AGESA_CFLAGS := $(AGESA_CFLAGS)
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CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS)
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CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS)
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CC_postcar:= $(CC_postcar) -I$(AGESA_ROOT)/binaryPI
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CC_postcar:= $(CC_postcar) -I$(src)/southbridge/amd/pi/hudson -I$(AGESA_ROOT)/binaryPI
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CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS)
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CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS)
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