sb/amd/pi/hudson: Enable use of common GPIO API

The code in soc/amd/common has an implementation of
GPIO register space that is compatible with the hardware
sb/amd/pi/hudson supports.

Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Kyösti Mälkki 2020-06-23 21:36:14 +03:00 committed by Hung-Te Lin
parent 219caf8358
commit b8cb142ccd
4 changed files with 22 additions and 1 deletions

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@ -19,6 +19,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
select HAVE_CF9_RESET_PREPARE
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
config EHCI_BAR

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@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SOC_GPIO_H
#define SOC_GPIO_H
/* <soc/gpio.h> must provide gpio_t. */
#include <amdblocks/gpio_banks.h>
#endif /* SOC_GPIO_H */

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@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SOC_SMI_H
#define SOC_SMI_H
#define SMI_SCI_TRIG 0x08
#define SMI_SCI_LEVEL 0x0c
#define SMI_SCI_STATUS 0x10
#define SMI_SCI_EN 0x14
#endif /* SOC_SMI_H */

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@ -76,7 +76,7 @@ export AGESA_CFLAGS := $(AGESA_CFLAGS)
CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS)
CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_postcar:= $(CC_postcar) -I$(AGESA_ROOT)/binaryPI
CC_postcar:= $(CC_postcar) -I$(src)/southbridge/amd/pi/hudson -I$(AGESA_ROOT)/binaryPI
CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS)