mainboard/asus/kgpe-d16: Update DSDT with new devices and bump version
Change-Id: I15fedb067f1911799f7528b60b8754f2984b38ec Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13161 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
This commit is contained in:
Timothy Pearson
Martin Roth
parent
448e386309
commit
b8d746fd13
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@ -33,7 +33,7 @@
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DefinitionBlock (
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"DSDT.AML", /* Output filename */
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"DSDT", /* Signature */
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0x02, /* DSDT Revision, needs to be 2 for 64bit */
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0x03, /* DSDT Revision, needs to be 2 or higher for 64bit */
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"ASUS ", /* OEMID */
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"COREBOOT", /* TABLE ID */
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0x00000001 /* OEM Revision */
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@ -47,9 +47,8 @@ DefinitionBlock (
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Name(OSV, Ones) /* Assume nothing */
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Name(PICM, One) /* Assume APIC */
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/* HPET control */
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Name (SHPB, 0xFED00000)
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Name (SHPL, 0x1000)
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/* HPET enable */
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Name (HPTE, 0x1)
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/* Define power states */
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Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) /* Normal operation */
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@ -126,12 +125,13 @@ DefinitionBlock (
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/* Root of the bus hierarchy */
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Scope (\_SB)
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{
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/* Top southbridge PCI device (SR5690) */
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/* Top southbridge PCI device (SR5690 + SP5100) */
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Device (PCI0)
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{
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/* BUS0 root bus */
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Name (_HID, EisaId ("PNP0A03"))
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Name (_HID, EisaId ("PNP0A08")) /* PCI-e root bus (SR5690) */
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Name (_CID, EisaId ("PNP0A03")) /* PCI root bus (SP5100) */
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Name (_ADR, 0x00180001)
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Name (_UID, 0x00)
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@ -490,6 +490,78 @@ DefinitionBlock (
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Name (_HID, EisaId ("PNP0A05"))
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Name (_ADR, 0x00140003)
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/* Real Time Clock Device */
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Device(RTC0) {
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Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
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Name(BUF0, ResourceTemplate() {
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IO(Decode16, 0x0070, 0x0070, 0x01, 0x02)
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})
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Name(BUF1, ResourceTemplate() {
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IRQNoFlags() { 8 }
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IO(Decode16, 0x0070, 0x0070, 0x01, 0x02)
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})
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Method(_CRS, 0) {
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If(HPTE) {
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Return(BUF0)
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}
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Return(BUF1)
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}
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}
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Device(TMR) { /* Timer */
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Name(_HID,EISAID("PNP0100")) /* System Timer */
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Name(BUF0, ResourceTemplate() {
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IO(Decode16, 0x0040, 0x0040, 0x01, 0x04)
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})
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Name(BUF1, ResourceTemplate() {
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IRQNoFlags() { 0 }
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IO(Decode16, 0x0040, 0x0040, 0x01, 0x04)
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})
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Method(_CRS, 0) {
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If(HPTE) {
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Return(BUF0)
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}
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Return(BUF1)
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}
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}
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Device(SPKR) { /* Speaker */
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Name(_HID,EISAID("PNP0800")) /* AT style speaker */
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Name(_CRS, ResourceTemplate() {
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IO(Decode16, 0x0061, 0x0061, 0, 1)
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})
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}
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Device(PIC) {
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Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
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Name(_CRS, ResourceTemplate() {
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IRQNoFlags() { 2 }
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IO(Decode16,0x0020, 0x0020, 0, 2)
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IO(Decode16,0x00A0, 0x00A0, 0, 2)
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})
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}
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Device(MAD) { /* 8257 DMA */
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Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
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Name(_CRS, ResourceTemplate() {
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DMA(Compatibility,BusMaster,Transfer8){4}
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IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
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IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
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IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
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IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
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IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
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IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
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}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
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}
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Device(COPR) {
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Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
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Name(_CRS, ResourceTemplate() {
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IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
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IRQNoFlags(){13}
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})
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}
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#include "../../../drivers/pc80/ps2_controller.asl"
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/* UART 1 */
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@ -515,34 +587,27 @@ DefinitionBlock (
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})
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}
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}
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}
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/* High Precision Event Timer */
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Device (HPET)
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/* High Precision Event Timer */
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Device (HPET)
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{
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Name (_HID, EisaId ("PNP0103"))
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Name (CRS, ResourceTemplate ()
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{
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Name (_HID, EisaId ("PNP0103"))
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Name (CRS, ResourceTemplate ()
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{
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Memory32Fixed (ReadOnly,
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0x00000000,
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0x00001000,
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_Y02)
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IRQNoFlags () {0}
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IRQNoFlags () {8}
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})
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Method (_STA, 0, NotSerialized)
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{
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Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400)
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})
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Method (_STA, 0)
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{
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If(HPTE) {
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Return (0x0F)
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}
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Method (_CRS, 0, NotSerialized)
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{
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CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT1)
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CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._LEN, HPT2)
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Store (SHPB, HPT1)
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Store (SHPL, HPT2)
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Return (CRS)
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}
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Return (0x0)
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}
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Method(_CRS, 0)
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{
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Return(CRS)
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}
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}
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/* 0:14.4 PCI Bridge */
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