soc/intel/quark: Add the verstage files

Add the files to support verstage for vboot.

TEST=Build and run on Galileo Gen2

Change-Id: Icf87075012c08cf581c17d579e0763888c707265
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18040
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>

src/soc/intel/quark/Makefile.inc

@@ -25,6 +25,11 @@ bootblock-y += reg_access.c
 bootblock-y += tsc_freq.c
 bootblock-y += uart_common.c
 
+verstage-y += i2c.c
+verstage-y += reg_access.c
+verstage-y += tsc_freq.c
+verstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
+
 romstage-y += i2c.c
 romstage-y += memmap.c
 romstage-y += reg_access.c