mediatek/mt8183: fix mode register setting fail issue
The mode register setting of DRAM may fail without some delay after each MR write. BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: I51785e90b2014994be5018bfe543245d44626242 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32284 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Huayang Duan
Patrick Georgi
parent
16ad2d70ca
commit
b8f65ad68a
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@ -14,6 +14,7 @@
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*/
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#include <device/mmio.h>
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#include <delay.h>
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#include <soc/emi.h>
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#include <soc/dramc_pi_api.h>
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#include <soc/dramc_register.h>
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@ -24,7 +25,7 @@ struct reg_init_value {
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u32 value;
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};
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struct reg_init_value dramc_init_sequence[] = {
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static struct reg_init_value dramc_init_sequence[] = {
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{&mt8183_infracfg->dramc_wbr, 0x00000000},
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{&ch[0].ao.refctrl0, 0x20712000},
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{&ch[1].ao.refctrl0, 0x20712000},
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@ -620,7 +621,52 @@ struct reg_init_value dramc_init_sequence[] = {
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{&ch[1].phy.shu[0].rk[1].b[1].dq[1], 0x22000000},
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{&ch[1].phy.shu[0].b[0].dll[1], 0x00022501},
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/* dramc mode register init */
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/* update the ac timing */
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{&ch[0].ao.shu[0].actim[0], 0x06020c07},
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{&ch[0].ao.shu[0].actim[1], 0x10080501},
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{&ch[0].ao.shu[0].actim[2], 0x07070201},
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{&ch[0].ao.shu[0].actim[3], 0x6164002c},
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{&ch[0].ao.shu[0].actim[4], 0x22650077},
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{&ch[0].ao.shu[0].actim[5], 0x0a000c0b},
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{&ch[0].ao.shu[0].actim_xrt, 0x05030609},
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{&ch[0].ao.shu[0].ac_time_05t, 0x000106e1},
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{&ch[0].ao.catraining1, 0x0b000000},
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{&ch[0].ao.shu[0].rk[0].dqsctl, 0x00000004},
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{&ch[0].ao.shu[0].rk[1].dqsctl, 0x00000004},
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{&ch[0].ao.shu[0].odtctrl, 0xc001004f},
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{&ch[0].ao.shu[0].conf[1], 0x34000d0f},
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{&ch[0].ao.shu[0].conf[2], 0x9007640f},
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{&ch[0].ao.shu[0].scintv, 0x4e39eb36},
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{&ch[0].ao.shu[0].ckectrl, 0x33210000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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{&ch[0].ao.shu[0].rankctl, 0x64300003},
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{&ch[0].ao.shu[0].rankctl, 0x64301203},
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{&ch[1].ao.shu[0].actim[0], 0x06020c07},
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{&ch[1].ao.shu[0].actim[1], 0x10080501},
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{&ch[1].ao.shu[0].actim[2], 0x07070201},
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{&ch[1].ao.shu[0].actim[3], 0x6164002c},
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{&ch[1].ao.shu[0].actim[4], 0x22650077},
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{&ch[1].ao.shu[0].actim[5], 0x0a000c0b},
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{&ch[1].ao.shu[0].actim_xrt, 0x05030609},
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{&ch[1].ao.shu[0].ac_time_05t, 0x000106e1},
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{&ch[1].ao.catraining1, 0x0b000000},
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{&ch[1].ao.shu[0].rk[0].dqsctl, 0x00000004},
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{&ch[1].ao.shu[0].rk[1].dqsctl, 0x00000004},
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{&ch[1].ao.shu[0].odtctrl, 0xc001004f},
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{&ch[1].ao.shu[0].conf[1], 0x34000d0f},
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{&ch[1].ao.shu[0].conf[2], 0x9007640f},
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{&ch[1].ao.shu[0].scintv, 0x4e39eb36},
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{&ch[1].ao.shu[0].ckectrl, 0x33210000},
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{&ch[1].ao.ckectrl, 0x88d02440},
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{&ch[1].ao.shu[0].rankctl, 0x64300003},
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{&ch[1].ao.shu[0].rankctl, 0x64301203},
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{&ch[0].ao.arbctl, 0x00000c80},
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{&ch[0].ao.rstmask, 0x00000000},
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{&ch[0].ao.arbctl, 0x00000c80},
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};
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static struct reg_init_value dramc_mode_reg_init_sequence[] = {
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/* dramc power on sequence */
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{&ch[0].phy.misc_ctrl1, 0x8100908c},
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{&ch[1].phy.misc_ctrl1, 0x8100908c},
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{&ch[0].ao.ckectrl, 0x88d02480},
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@ -632,6 +678,8 @@ struct reg_init_value dramc_init_sequence[] = {
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{&ch[0].ao.ckectrl, 0x88d02440},
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{&ch[1].ao.ckectrl, 0x88d02440},
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{&ch[0].ao.mrs, 0x00000000},
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/* CH0 dramc ZQ Calibration */
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{&ch[0].ao.dramc_pd_ctrl, 0xc4000107},
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{&ch[0].ao.ckectrl, 0x88d02440},
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{&ch[0].ao.mrs, 0x00000000},
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@ -641,70 +689,104 @@ struct reg_init_value dramc_init_sequence[] = {
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{&ch[0].ao.mrs, 0x00000000},
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{&ch[0].ao.dramc_pd_ctrl, 0xc4000107},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR13 */
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{&ch[0].ao.mrs, 0x00000d18},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR12 */
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{&ch[0].ao.mrs, 0x00000c5d},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR1 */
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{&ch[0].ao.mrs, 0x00000156},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR2 */
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{&ch[0].ao.mrs, 0x0000020b},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR11 */
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{&ch[0].ao.mrs, 0x00000b00},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR22 */
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{&ch[0].ao.mrs, 0x00001638},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR14 */
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{&ch[0].ao.mrs, 0x00000e5d},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR3 */
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{&ch[0].ao.mrs, 0x00000330},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR13 */
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{&ch[0].ao.mrs, 0x00000d58},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR12 */
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{&ch[0].ao.mrs, 0x00000c5d},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR1 */
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{&ch[0].ao.mrs, 0x00000156},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR2 */
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{&ch[0].ao.mrs, 0x0000022d},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR11 */
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{&ch[0].ao.mrs, 0x00000b23},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR22 */
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{&ch[0].ao.mrs, 0x00001634},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR14 */
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{&ch[0].ao.mrs, 0x00000e10},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR3 */
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{&ch[0].ao.mrs, 0x00000330},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* dramc ZQ Calibration */
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{&ch[0].ao.mrs, 0x01000330},
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{&ch[0].ao.dramc_pd_ctrl, 0xc4000107},
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{&ch[0].ao.ckectrl, 0x88d02440},
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@ -715,76 +797,112 @@ struct reg_init_value dramc_init_sequence[] = {
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{&ch[0].ao.mrs, 0x01000330},
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{&ch[0].ao.dramc_pd_ctrl, 0xc4000107},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR13 */
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{&ch[0].ao.mrs, 0x01000d18},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR12 */
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{&ch[0].ao.mrs, 0x01000c5d},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR1 */
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{&ch[0].ao.mrs, 0x01000156},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR2 */
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{&ch[0].ao.mrs, 0x0100020b},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR11 */
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{&ch[0].ao.mrs, 0x01000b00},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR22 */
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{&ch[0].ao.mrs, 0x01001638},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR14 */
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{&ch[0].ao.mrs, 0x01000e5d},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR3 */
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{&ch[0].ao.mrs, 0x01000330},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR13 */
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{&ch[0].ao.mrs, 0x01000d58},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR12 */
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{&ch[0].ao.mrs, 0x01000c5d},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR1 */
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{&ch[0].ao.mrs, 0x01000156},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR2 */
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{&ch[0].ao.mrs, 0x0100022d},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR11 */
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{&ch[0].ao.mrs, 0x01000b23},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR22 */
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{&ch[0].ao.mrs, 0x01001634},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR14 */
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{&ch[0].ao.mrs, 0x01000e10},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR3 */
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{&ch[0].ao.mrs, 0x01000330},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR13 */
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{&ch[0].ao.mrs, 0x00000330},
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{&ch[0].ao.ckectrl, 0x88d02440},
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{&ch[0].ao.mrs, 0x00000dd8},
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{&ch[0].ao.spcmd, 0x00000001},
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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/* MR13 */
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{&ch[0].ao.mrs, 0x01000dd8},
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{&ch[0].ao.ckectrl, 0x88d02440},
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{&ch[0].ao.mrs, 0x01000dd8},
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@ -792,9 +910,12 @@ struct reg_init_value dramc_init_sequence[] = {
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{&ch[0].ao.spcmd, 0x00000000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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{&ch[0].ao.mrs, 0x01000dd8},
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{&ch[0].ao.shu[0].hwset_mr13, 0x00d8000d},
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{&ch[0].ao.shu[0].hwset_vrcg, 0x00d8000d},
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{&ch[0].ao.shu[0].hwset_mr2, 0x002d0002},
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/* CH1 dramc ZQ Calibration */
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{&ch[1].ao.mrs, 0x00000000},
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{&ch[1].ao.dramc_pd_ctrl, 0xc4000107},
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{&ch[1].ao.ckectrl, 0x88d02440},
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@ -961,49 +1082,6 @@ struct reg_init_value dramc_init_sequence[] = {
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{&ch[1].ao.shu[0].hwset_mr2, 0x002d0002},
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{&ch[0].ao.mrs, 0x00000dd8},
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{&ch[1].ao.mrs, 0x00000dd8},
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/* update the ac timing */
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{&ch[0].ao.shu[0].actim[0], 0x06020c07},
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{&ch[0].ao.shu[0].actim[1], 0x10080501},
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{&ch[0].ao.shu[0].actim[2], 0x07070201},
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{&ch[0].ao.shu[0].actim[3], 0x6164002c},
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{&ch[0].ao.shu[0].actim[4], 0x22650077},
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{&ch[0].ao.shu[0].actim[5], 0x0a000c0b},
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{&ch[0].ao.shu[0].actim_xrt, 0x05030609},
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{&ch[0].ao.shu[0].ac_time_05t, 0x000106e1},
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{&ch[0].ao.catraining1, 0x0b000000},
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{&ch[0].ao.shu[0].rk[0].dqsctl, 0x00000004},
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{&ch[0].ao.shu[0].rk[1].dqsctl, 0x00000004},
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{&ch[0].ao.shu[0].odtctrl, 0xc001004f},
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{&ch[0].ao.shu[0].conf[1], 0x34000d0f},
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{&ch[0].ao.shu[0].conf[2], 0x9007640f},
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{&ch[0].ao.shu[0].scintv, 0x4e39eb36},
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{&ch[0].ao.shu[0].ckectrl, 0x33210000},
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{&ch[0].ao.ckectrl, 0x88d02440},
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{&ch[0].ao.shu[0].rankctl, 0x64300003},
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{&ch[0].ao.shu[0].rankctl, 0x64301203},
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{&ch[1].ao.shu[0].actim[0], 0x06020c07},
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{&ch[1].ao.shu[0].actim[1], 0x10080501},
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{&ch[1].ao.shu[0].actim[2], 0x07070201},
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{&ch[1].ao.shu[0].actim[3], 0x6164002c},
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{&ch[1].ao.shu[0].actim[4], 0x22650077},
|
||||
{&ch[1].ao.shu[0].actim[5], 0x0a000c0b},
|
||||
{&ch[1].ao.shu[0].actim_xrt, 0x05030609},
|
||||
{&ch[1].ao.shu[0].ac_time_05t, 0x000106e1},
|
||||
{&ch[1].ao.catraining1, 0x0b000000},
|
||||
{&ch[1].ao.shu[0].rk[0].dqsctl, 0x00000004},
|
||||
{&ch[1].ao.shu[0].rk[1].dqsctl, 0x00000004},
|
||||
{&ch[1].ao.shu[0].odtctrl, 0xc001004f},
|
||||
{&ch[1].ao.shu[0].conf[1], 0x34000d0f},
|
||||
{&ch[1].ao.shu[0].conf[2], 0x9007640f},
|
||||
{&ch[1].ao.shu[0].scintv, 0x4e39eb36},
|
||||
{&ch[1].ao.shu[0].ckectrl, 0x33210000},
|
||||
{&ch[1].ao.ckectrl, 0x88d02440},
|
||||
{&ch[1].ao.shu[0].rankctl, 0x64300003},
|
||||
{&ch[1].ao.shu[0].rankctl, 0x64301203},
|
||||
{&ch[0].ao.arbctl, 0x00000c80},
|
||||
{&ch[0].ao.rstmask, 0x00000000},
|
||||
{&ch[0].ao.arbctl, 0x00000c80},
|
||||
};
|
||||
|
||||
void dramc_init(void)
|
||||
|
|
@ -1011,4 +1089,10 @@ void dramc_init(void)
|
|||
for (int i = 0; i < ARRAY_SIZE(dramc_init_sequence); i++)
|
||||
write32(dramc_init_sequence[i].addr,
|
||||
dramc_init_sequence[i].value);
|
||||
|
||||
for (int i = 0; i < ARRAY_SIZE(dramc_mode_reg_init_sequence); i++) {
|
||||
write32(dramc_mode_reg_init_sequence[i].addr,
|
||||
dramc_mode_reg_init_sequence[i].value);
|
||||
udelay(2);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue