High tables don't have to be on node 0 on K8. Make it less restrictive.
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
parent
5ec3ead6dc
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b904d7bce9
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@ -0,0 +1,273 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Vincent Legoll <vincent.legoll@gmail.com>
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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*/
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/*
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* K8 northbridge utilities (dump routing registers).
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* Designed to be called at any time.
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* It can be called before RAM is set up by including this file.
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* It can be called after RAM is set up by including amdk8.h and enabling the
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* compilation of this file in src/northbridge/amd/amdk8/Makefile.inc.
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*/
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#ifndef __PRE_RAM__
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#include <console/console.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#endif
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#include "amdk8.h"
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/* Function 1 */
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/* the DRAM, MMIO,and PCIIO routing are 64-bit registers, hence the ending at
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* 0x78, 0xb8, and 0xd8
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*/
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#define DRAM_ROUTE_START 0x40
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#define DRAM_ROUTE_END 0x78
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#define MMIO_ROUTE_START 0x80
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#define MMIO_ROUTE_END 0xb8
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#define PCIIO_ROUTE_START 0xc0
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#define PCIIO_ROUTE_END 0xd8
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#define CONFIG_ROUTE_START 0xe0
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#define CONFIG_ROUTE_END 0xec
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#define PCI_IO_BASE0 0xc0
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#define PCI_IO_BASE1 0xc8
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#define PCI_IO_BASE2 0xd0
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#define PCI_IO_BASE3 0xd8
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#define PCI_IO_BASE_VGA_EN (1 << 4)
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#define PCI_IO_BASE_NO_ISA (1 << 5)
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#define BITS(r, shift, mask) (((r>>shift)&mask))
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/**
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* Return "R" if the register has read-enable bit set.
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*/
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static const char *re(u32 i)
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{
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return ((i & 1) ? "R" : "");
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}
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/**
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* Return "W" if the register has write-enable bit set.
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*/
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static const char *we(u32 i)
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{
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return ((i & 1) ? "W" : "");
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}
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/**
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* Return a string containing the interleave settings.
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*/
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static const char *ileave(u32 base)
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{
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switch ((base >> 8) & 7) {
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case 0:
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return "No interleave";
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case 1:
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return "2 nodes";
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case 3:
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return "4 nodes";
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case 7:
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return "8 nodes";
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default:
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return "Reserved";
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}
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}
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/**
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* Return the node number.
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* For one case (config registers) these are not the right bit fields.
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*/
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static int r_node(u32 reg)
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{
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return BITS(reg, 0, 0x7);
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}
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/**
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* Return the link number.
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* For one case (config registers) these are not the right bit fields.
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*/
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static int r_link(u32 reg)
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{
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return BITS(reg, 4, 0x3);
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}
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/**
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* Print the DRAM routing info for one base/limit pair.
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*
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* Show base, limit, dest node, dest link on that node, read and write
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* enable, and interleave information.
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*
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* @param level Printing level
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* @param which Register number
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* @param base Base register
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* @param lim Limit register
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*/
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static void showdram(int level, u8 which, u32 base, u32 lim)
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{
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printk(level, "DRAM(%02x)%010llx-%010llx, ->(%d), %s, %s, %s, %d\n",
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which, (((u64) base & 0xffff0000) << 8),
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(((u64) lim & 0xffff0000) << 8) + 0xffffff,
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r_node(lim), re(base), we(base), ileave(base), (lim >> 8) & 3);
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}
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/**
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* Print the config routing info for a config register.
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*
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* Show base, limit, dest node, dest link on that node, read and write
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* enable, and device number compare enable
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*
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* @param level Printing level
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* @param which Register number
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* @param reg Config register
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*/
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static void showconfig(int level, u8 which, u32 reg)
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{
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/* Don't use r_node() and r_link() here. */
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printk(level, "CONFIG(%02x)%02x-%02x ->(%d,%d),%s %s (%s numbers)\n",
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which, BITS(reg, 16, 0xff), BITS(reg, 24, 0xff),
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BITS(reg, 4, 0x7), BITS(reg, 8, 0x3),
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re(reg), we(reg),
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BITS(reg, 2, 0x1)?"dev":"bus");
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}
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/**
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* Print the PCIIO routing info for one base/limit pair.
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*
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* Show base, limit, dest node, dest link on that node, read and write
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* enable, and VGA and ISA Enable.
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*
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* @param level Printing level
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* @param which Register number
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* @param base Base register
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* @param lim Limit register
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*/
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static void showpciio(int level, u8 which, u32 base, u32 lim)
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{
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printk(level, "PCIIO(%02x)%07x-%07x, ->(%d,%d), %s, %s,VGA %d ISA %d\n",
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which, BITS(base, 12, 0x3fff) << 12,
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(BITS(lim, 12, 0x3fff) << 12) + 0xfff, r_node(lim), r_link(lim),
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re(base), we(base), BITS(base, 4, 0x1), BITS(base, 5, 0x1));
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}
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/**
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* Print the MMIO routing info for one base/limit pair.
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*
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* Show base, limit, dest node, dest link on that node, read and write
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* enable, and CPU Disable, Lock, and Non-posted.
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*
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* @param level Printing level
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* @param which Register number
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* @param base Base register
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* @param lim Limit register
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*/
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static void showmmio(int level, u8 which, u32 base, u32 lim)
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{
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printk(level, "MMIO(%02x)%010llx-%010llx, ->(%d,%d), %s, %s, "
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"CPU disable %d, Lock %d, Non posted %d\n",
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which, ((u64) BITS(base, 0, 0xffffff00)) << 8,
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(((u64) BITS(lim, 0, 0xffffff00)) << 8) + 0xffff, r_node(lim),
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r_link(lim), re(base), we(base), BITS(base, 4, 0x1),
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BITS(base, 7, 0x1), BITS(lim, 7, 0x1));
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}
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/**
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* Show all DRAM routing registers. This function is callable at any time.
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*
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* @param level The debug level.
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* @param dev A 32-bit number in the standard bus/dev/fn format which is used
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* raw config space.
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*/
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static void showalldram(int level, device_t dev)
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{
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u8 reg;
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for (reg = DRAM_ROUTE_START; reg <= DRAM_ROUTE_END; reg += 8) {
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u32 base = pci_read_config32(dev, reg);
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u32 lim = pci_read_config32(dev, reg + 4);
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if (base || lim!=(reg-DRAM_ROUTE_START)/8)
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showdram(level, reg, base, lim);
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}
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}
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/**
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* Show all MMIO routing registers. This function is callable at any time.
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*
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* @param level The debug level.
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* @param dev A 32-bit number in the standard bus/dev/fn format which is used
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* raw config space.
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*/
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static void showallmmio(int level, device_t dev)
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{
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u8 reg;
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for (reg = MMIO_ROUTE_START; reg <= MMIO_ROUTE_END; reg += 8) {
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u32 base = pci_read_config32(dev, reg);
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u32 lim = pci_read_config32(dev, reg + 4);
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if (base || lim)
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showmmio(level, reg, base, lim);
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}
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}
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/**
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* Show all PCIIO routing registers. This function is callable at any time.
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*
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* @param level The debug level.
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* @param dev A 32-bit number in the standard bus/dev/fn format which is used
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* raw config space.
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*/
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static void showallpciio(int level, device_t dev)
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{
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u8 reg;
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for (reg = PCIIO_ROUTE_START; reg <= PCIIO_ROUTE_END; reg += 8) {
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u32 base = pci_read_config32(dev, reg);
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u32 lim = pci_read_config32(dev, reg + 4);
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if (base || lim)
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showpciio(level, reg, base, lim);
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}
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}
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/**
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* Show all config routing registers. This function is callable at any time.
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*
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* @param level The debug level.
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* @param dev A 32-bit number in the standard bus/dev/fn format which is used
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* raw config space.
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*/
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static void showallconfig(int level, device_t dev)
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{
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u8 reg;
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for (reg = CONFIG_ROUTE_START; reg <= CONFIG_ROUTE_END; reg += 4) {
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u32 val = pci_read_config32(dev, reg);
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if (val)
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showconfig(level, reg, val);
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}
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}
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/**
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* Show all routing registers. This function is callable at any time.
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*
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* @param level The debug level.
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* @param dev A 32-bit number in the standard bus/dev/fn format which is used
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* raw config space.
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*/
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void showallroutes(int level, device_t dev)
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{
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showalldram(level, dev);
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showallmmio(level, dev);
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showallpciio(level, dev);
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showallconfig(level, dev);
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}
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@ -1021,7 +1021,7 @@ static void amdk8_domain_set_resources(device_t dev)
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idx += 0x10;
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idx += 0x10;
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sizek -= pre_sizek;
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sizek -= pre_sizek;
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#if CONFIG_WRITE_HIGH_TABLES==1
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#if CONFIG_WRITE_HIGH_TABLES==1
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if (i==0 && high_tables_base==0) {
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if (high_tables_base==0) {
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/* Leave some space for ACPI, PIRQ and MP tables */
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/* Leave some space for ACPI, PIRQ and MP tables */
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#if CONFIG_GFXUMA == 1
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#if CONFIG_GFXUMA == 1
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high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
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high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
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@ -1061,7 +1061,7 @@ static void amdk8_domain_set_resources(device_t dev)
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#if CONFIG_WRITE_HIGH_TABLES==1
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#if CONFIG_WRITE_HIGH_TABLES==1
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printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
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printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
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i, mmio_basek, basek, limitk);
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i, mmio_basek, basek, limitk);
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if (i==0 && high_tables_base==0) {
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if (high_tables_base==0) {
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/* Leave some space for ACPI, PIRQ and MP tables */
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/* Leave some space for ACPI, PIRQ and MP tables */
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#if CONFIG_GFXUMA == 1
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#if CONFIG_GFXUMA == 1
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high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
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high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
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