From b9165199c32ace5d661d28b5afb500b5451efc9b Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 22 Oct 2023 12:10:35 -0500 Subject: [PATCH] mb/prodrive/hermes: Rework UART devicetree entry Rework the UART devicetree entry so that it doesn't conflict with the to-be-added chipset devicetree for CNL. This should be functionally equivalent to the previous entry, but needs testing to verify. Change-Id: Iae60cb8e0746e7dc2928da3687762b81928fb5f0 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/78546 Reviewed-by: Angel Pons Reviewed-by: Eric Lai Reviewed-by: Martin L Roth Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/mainboard/prodrive/hermes/devicetree.cb | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 8c2dbda38e..024b97d02b 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -170,11 +170,12 @@ chip soc/intel/cannonlake # This device does not have any function on CNP-H, but it needs # to be here so that the resource allocator is aware of UART 2. device pci 19.0 hidden end - chip soc/intel/common/block/uart - device pci 19.2 hidden + device pci 19.2 hidden + chip soc/intel/common/block/uart register "devid" = "PCI_DID_INTEL_CNP_H_UART2" - end # UART #2, in ACPI mode - end + device generic 0 hidden end + end + end # UART #2, in ACPI mode device pci 1b.4 on # PCIe root port 21 (Slot 1) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" register "PcieRpEnable[20]" = "1"