superio/ite/it8712f: Depreciate model specific early_serial.c
We now have common ite_*_*() functions for romstage and hence no longer require the model specific portion of this superio support. Change-Id: I30400abf27008a88072673075bba445f100d9ad3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5838 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
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@ -30,7 +30,6 @@
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#include "lib/delay.c"
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#include "cpu/x86/lapic.h"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "superio/ite/it8712f/early_serial.c"
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#include <spd.h>
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#include "cpu/x86/bist.h"
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#include "northbridge/amd/amdk8/setup_resource_map.c"
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@ -18,5 +18,4 @@
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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romstage-$(CONFIG_SUPERIO_ITE_IT8712F) += early_serial.c
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ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c
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@ -1,76 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <device/pnp.h>
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#include <stdint.h>
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#include "it8712f.h"
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/* The base address is 0x2e or 0x4e, depending on config bytes. */
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#define SIO_BASE 0x2e
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#define SIO_INDEX SIO_BASE
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#define SIO_DATA (SIO_BASE + 1)
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/* Global configuration registers. */
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#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
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#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
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#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
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#define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
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#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */
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#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
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static void it8712f_sio_write(u8 ldn, u8 index, u8 value)
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{
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outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
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outb(ldn, SIO_DATA);
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outb(index, SIO_BASE);
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outb(value, SIO_DATA);
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}
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static void it8712f_enter_conf(void)
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{
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u16 port = 0x2e; /* TODO: Don't hardcode! */
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outb(0x87, port);
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outb(0x01, port);
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outb(0x55, port);
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outb((port == 0x4e) ? 0xaa : 0x55, port);
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}
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static void it8712f_exit_conf(void)
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{
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it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
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}
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/*
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* We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2!
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*
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* LDN 7, reg 0x2a - needed for S3, or memory power will be cut off.
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*
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* Enable 3VSBSW#. (For System Suspend-to-RAM)
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* 0: 3VSBSW# will be always inactive.
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* 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
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*/
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void it8712f_enable_3vsbsw(void)
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{
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it8712f_enter_conf();
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it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80);
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it8712f_exit_conf();
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}
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@ -35,6 +35,4 @@
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#define IT8712F_GAME 0x09 /* GAME port */
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#define IT8712F_IR 0x0a /* Consumer IR */
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void it8712f_enable_3vsbsw(void);
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#endif /* SUPERIO_ITE_IT8712F_H */
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