diff --git a/src/mainboard/google/zork/variants/dirinboz/gpio.c b/src/mainboard/google/zork/variants/dirinboz/gpio.c
index 12b303a9c5..8da85b6720 100644
--- a/src/mainboard/google/zork/variants/dirinboz/gpio.c
+++ b/src/mainboard/google/zork/variants/dirinboz/gpio.c
@@ -8,6 +8,10 @@
 #include <ec/google/chromeec/ec.h>
 
 static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
+	/* PEN_DETECT_ODL - no used */
+	PAD_NC(GPIO_4),
+	/* PEN_POWER_EN - no used */
+	PAD_NC(GPIO_5),
 	/* TP */
 	PAD_NC(GPIO_32),
 	/* EN_DEV_BEEP_L */
@@ -16,6 +20,13 @@ static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
 	PAD_GPO(GPIO_140, HIGH),
 };
 
+static const struct soc_amd_gpio dirinboz_gpio_set_stage_ram[] = {
+	/* PEN_DETECT_ODL - no used */
+	PAD_NC(GPIO_4),
+	/* PEN_POWER_EN - no used */
+	PAD_NC(GPIO_5),
+};
+
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
 {
 	uint32_t board_version;
@@ -33,6 +44,6 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
 		return bid_1_gpio_set_stage_ram;
 	}
 
-	*size = 0;
-	return NULL;
+	*size = ARRAY_SIZE(dirinboz_gpio_set_stage_ram);
+	return dirinboz_gpio_set_stage_ram;
 }