mb/asus/p8z77-m_pro: Switch to overridetree setup

Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8Z77-M PRO
remains identical when not adding the .config file in it.

Change-Id: I7f1d93e500153a9821e7ddb693d77c864c879f0d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/mainboard/asus/p8z77-series/Kconfig

@@ -29,22 +29,10 @@ config MAINBOARD_PART_NUMBER
 	default "P8Z77-M PRO" if BOARD_ASUS_P8Z77_M_PRO
 	default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2
 
-# TODO: remove once all boards use overridetrees
-if BOARD_ASUS_P8Z77_M_PRO
-
-config DEVICETREE
-	string
-	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
-
-endif
-if !BOARD_ASUS_P8Z77_M_PRO
-
 config OVERRIDE_DEVICETREE
 	string
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
-endif
-
 config CMOS_DEFAULT_FILE
 	default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.default"
 

src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/overridetree.cb

@@ -1,42 +1,13 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 chip northbridge/intel/sandybridge
-	device cpu_cluster 0 on
-		chip cpu/intel/model_206ax
-			register "acpi_c1" = "1"
-			register "acpi_c2" = "3"
-			register "acpi_c3" = "5"
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
-	end
 	device domain 0 on
 		subsystemid 0x1043 0x84ca inherit
-		device pci 00.0 on  end	# Host bridge
+		chip southbridge/intel/bd82x6x
-		device pci 01.0 on  end	# PCIe Bridge for discrete graphics
-		device pci 02.0 on  end	# Internal graphics VGA controller
-
-		chip southbridge/intel/bd82x6x	# Intel Series 6 Cougar Point PCH
-			register "c2_latency" = "0x0065"
 			register "gen1_dec" = "0x000c0291"
 			register "gen4_dec" = "0x0000ff29"
 			register "pcie_port_coalesce" = "1"
-			register "sata_interface_speed_support" = "0x3" # 0x3=SATAIII
-			register "sata_port_map" = "0x3f" # Enable the six SATA ports
-			register "spi_lvscc" = "0x2005"
-			register "spi_uvscc" = "0x2005"
-			register "superspeed_capable_ports" = "0x0000000f"
-			register "xhci_overcurrent_mapping" = "0x00000c03"
-			register "xhci_switchable_ports" = "0x0000000f" # the 4 ports
 
-			device pci 14.0 on  end	# USB 3.0 Controller
-			device pci 16.0 on  end	# Management Engine Interface 1
-			device pci 16.1 off end	# Management Engine Interface 2
-			device pci 16.2 off end	# Management Engine IDE-R
-			device pci 16.3 off end	# Management Engine KT
-			device pci 19.0 off end	# Intel Gigabit Ethernet
-			device pci 1a.0 on  end	# USB2 EHCI 2
-			device pci 1b.0 on  end	# High Definition Audio controller
 			device pci 1c.0 on  end	# PCIe Port 1 PCIEX_16_3
 			device pci 1c.1 on  end	# PCIe Port 2 RTL8111F
 			device pci 1c.2 off end	# PCIe Port 3 unused
@@ -45,8 +16,7 @@ chip northbridge/intel/sandybridge
 			device pci 1c.5 on  end	# PCIe Port 6 ASM1042 USB3
 			device pci 1c.6 on  end	# PCIe Port 7 ASM1061 eSATA
 			device pci 1c.7 off end	# PCIe Port 8 unused
-			device pci 1d.0 on  end	# USB2 EHCI 1
+
-			device pci 1e.0 off end	# PCI bridge
 			device pci 1f.0 on	# LPC bridge
 				chip superio/nuvoton/nct6779d
 					device pnp 2e.1 off end	# Parallel
@@ -84,10 +54,6 @@ chip northbridge/intel/sandybridge
 					device pnp 4e.0 on end	# TPM
 				end
 			end
-			device pci 1f.2 on  end	# SATA Controller 1
-			device pci 1f.3 on  end	# SMBus
-			device pci 1f.5 off end	# SATA Controller 2
-			device pci 1f.6 off end	# Thermal
 		end
 	end
 end