mb/google/octopus: Override emmc DLL values for Ampton
New emmc DLL values for Ampton BUG=b:122307153 TEST=Boot to OS on 5 systems Change-Id: Iadd58d254f4bb384f483c2c3e5615f7569d5211c Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/31048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
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chip soc/intel/apollolake
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# EMMC Tx CMD Delay
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# Refer to EDS-Vol2-16.32.
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# [14:8] steps of delay for DDR mode, each 125ps.
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# [6:0] steps of delay for SDR mode, each 125ps.
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register "emmc_tx_cmd_cntl" = "0x505"
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# EMMC TX DATA Delay 1
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# Refer to EDS-Vol2-16.33.
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# [14:8] steps of delay for HS400, each 125ps.
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# [6:0] steps of delay for SDR104/HS200, each 125ps.
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register "emmc_tx_data_cntl1" = "0x0a0c"
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# EMMC TX DATA Delay 2
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# Refer to EDS-Vol2-16.34.
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# [30:24] steps of delay for SDR50, each 125ps.
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# [22:16] steps of delay for DDR50, each 125ps.
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# [14:8] steps of delay for SDR25/HS50, each 125ps.
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# [6:0] steps of delay for SDR12, each 125ps.
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register "emmc_tx_data_cntl2" = "0x1c292929"
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# EMMC RX CMD/DATA Delay 1
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# Refer to EDS-Vol2-16.35.
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# [30:24] steps of delay for SDR50, each 125ps.
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# [22:16] steps of delay for DDR50, each 125ps.
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# [14:8] steps of delay for SDR25/HS50, each 125ps.
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# [6:0] steps of delay for SDR12, each 125ps.
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register "emmc_rx_cmd_data_cntl1" = "0x001a1c1c"
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# EMMC RX CMD/DATA Delay 2
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# Refer to EDS-Vol2-16.37.
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# [17:16] stands for Rx Clock before Output Buffer
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# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
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# [6:0] steps of delay for HS200, each 125ps.
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register "emmc_rx_cmd_data_cntl2" = "0x10026"
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# EMMC Rx Strobe Delay
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# Refer to EDS-Vol2-16.36.
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# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps.
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# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps.
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register "emmc_rx_strobe_cntl" = "0x0a0a"
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register "common_soc_config" = "{
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.gspi[0] = {
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.speed_mhz = 1,
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