From b947b147348ee31285637e1c4f08c6e52e512f4d Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Thu, 27 Apr 2006 17:46:27 +0000 Subject: [PATCH] more code removal and removal of incorrect register settings. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/gx2/northbridge.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index 55dc4acc18..97067d4e70 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -132,6 +132,7 @@ setup_gx2_cache(void) int sizembytes, sizereg; sizembytes = sizeram(); +#ifdef NO printk_debug("enable_cache: enable for %dm bytes\n", sizembytes); /* build up the rconf word. */ /* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */ @@ -155,7 +156,7 @@ setup_gx2_cache(void) msr.hi = (val >> 32); printk_debug("msr will be set to %x:%x\n", msr.hi, msr.lo); wrmsr(CPU_RCONF_DEFAULT, msr); - +#endif enable_cache(); wbinvd(); return sizembytes; @@ -419,6 +420,7 @@ static void enable_dev(struct device *dev) cpubug(); chipsetinit(); //setup_gx2(); + setup_gx2_cache(); /* do this here for now -- this chip really breaks our device model */ setup_realmode_idt(); do_vsmbios();