This patch adds support for the Intel D810E2CB (i810e/ICH2) desktop board. Hurray, this is the first i810 board running CAR.
Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Joseph Smith
Joseph Smith
parent
40bffc22cd
commit
b94a79fa6a
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@ -23,3 +23,16 @@ config CPU_INTEL_SOCKET_FC_PGA370
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select CPU_INTEL_MODEL_68X
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select CPU_INTEL_MODEL_68X
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select MMX
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select MMX
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select SSE
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select SSE
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select USE_PRINTK_IN_CAR
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select USE_DCACHE_RAM
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select TINY_BOOTBLOCK
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config DCACHE_RAM_BASE
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hex
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default 0xffdf8000
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depends on CPU_INTEL_SOCKET_FC_PGA370
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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depends on CPU_INTEL_SOCKET_FC_PGA370
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@ -0,0 +1,52 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config BOARD_INTEL_D810E2CB
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bool "D810E2CB"
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select ARCH_X86
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select CPU_INTEL_SOCKET_FC_PGA370
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select NORTHBRIDGE_INTEL_I82810
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select SOUTHBRIDGE_INTEL_I82801BX
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select SUPERIO_SMSC_SMSCSUPERIO
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select HAVE_PIRQ_TABLE
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select UDELAY_TSC
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select BOARD_ROMSIZE_KB_512
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select HAVE_MAINBOARD_RESOURCES
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select GFXUMA
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config MAINBOARD_DIR
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string
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default intel/d810e2cb
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depends on BOARD_INTEL_D810E2CB
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config MAINBOARD_PART_NUMBER
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string
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default "D810E2CB"
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depends on BOARD_INTEL_D810E2CB
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config HAVE_OPTION_TABLE
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bool
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default n
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depends on BOARD_INTEL_D810E2CB
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config IRQ_SLOT_COUNT
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int
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default 7
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depends on BOARD_INTEL_D810E2CB
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations mainboard_ops;
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struct mainboard_config {};
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@ -0,0 +1,82 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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chip northbridge/intel/i82810 # Northbridge
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/socket_FC_PGA370 # CPU
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
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device pci 1.0 on end # Chipset Graphics Controller (CGC)
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chip southbridge/intel/i82801bx # Southbridge
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register "pirqa_routing" = "0x05"
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register "pirqb_routing" = "0x06"
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register "pirqc_routing" = "0x07"
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register "pirqd_routing" = "0x09"
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register "pirqe_routing" = "0x0a"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x0b"
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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device pci 1e.0 on end # PCI bridge
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device pci 1f.0 on # ISA bridge
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chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47M102)
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device pnp 4e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 4e.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 4
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end
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device pnp 4e.4 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 4e.5 off end # COM2
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device pnp 4e.7 on # PS/2 keyboard / mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # PS/2 keyboard interrupt
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irq 0x72 = 12 # PS/2 mouse interrupt
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end
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device pnp 4e.9 off end # Game port
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device pnp 4e.a on # Runtime registers
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io 0x60 = 0x800
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end
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device pnp 4e.b off end # MPU-401
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end
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end
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device pci 1f.1 on end # IDE
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device pci 1f.2 on end # USB
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device pci 1f.3 on end # SMbus
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device pci 1f.4 on end # USB
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device pci 1f.5 on end # Audio controller
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device pci 1f.6 off end # Modem controller
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end
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end
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end
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@ -0,0 +1,211 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define PME_DEV PNP_DEV(0x4e, 0x0a)
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#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
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/* Early mainboard specific GPIO setup. */
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static void mb_gpio_init(void)
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{
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device_t dev;
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uint16_t port;
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/* Southbridge GPIOs. */
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/* Set the LPC device statically. */
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dev = PCI_DEV(0x0, 0x1f, 0x0);
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/* Set the value for GPIO base address register and enable GPIO. */
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pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
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pci_write_config8(dev, GPIO_CNTL, 0x10);
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udelay(10);
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outl(0x1a203180, GPIO_BASE_ADDR + 0x00); /* GPIO_USE_SEL */
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outl(0x0000ffff, GPIO_BASE_ADDR + 0x04); /* GP_IO_SEL */
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outl(0x13bf0000, GPIO_BASE_ADDR + 0x0c); /* GP_LVL */
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outl(0x00040000, GPIO_BASE_ADDR + 0x18); /* GPO_BLINK */
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outl(0x000039ff, GPIO_BASE_ADDR + 0x2c); /* GPI_INV */
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/* Super I/O GPIOs. */
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dev = PME_DEV;
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port = dev >> 8;
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/* Enter the configuration state. */
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outb(0x55, port);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
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pnp_set_enable(dev, 1);
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/* GP10 - J1B1 */
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outl(0x01, PME_IO_BASE_ADDR + 0x23);
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/* GP11 - J1B2 */
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outl(0x01, PME_IO_BASE_ADDR + 0x24);
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/* GP12 - J2B1 */
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outl(0x01, PME_IO_BASE_ADDR + 0x25);
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/* GP13 - J2B2 */
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outl(0x01, PME_IO_BASE_ADDR + 0x26);
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/* GP14 - J1X */
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outl(0x01, PME_IO_BASE_ADDR + 0x27);
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/* GP15 - J1Y */
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outl(0x01, PME_IO_BASE_ADDR + 0x28);
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/* GP16 - J2X */
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outl(0x01, PME_IO_BASE_ADDR + 0x29);
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/* GP17 - J2Y */
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outl(0x01, PME_IO_BASE_ADDR + 0x2a);
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/* GP20 - 8042 P17 */
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outl(0x01, PME_IO_BASE_ADDR + 0x2b);
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/* GP21 - 8042 P16 */
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outl(0x00, PME_IO_BASE_ADDR + 0x2c);
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/* GP22 - 8042 P12 */
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outl(0x00, PME_IO_BASE_ADDR + 0x2d);
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/* GP24 */
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outl(0x00, PME_IO_BASE_ADDR + 0x2f);
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/* GP25 - MIDI_IN */
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outl(0x01, PME_IO_BASE_ADDR + 0x30);
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/* GP26 - MIDI_OUT */
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outl(0x01, PME_IO_BASE_ADDR + 0x31);
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/* GP27 - nIO_SMI */
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outl(0x04, PME_IO_BASE_ADDR + 0x32);
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/* GP30 - FAN_TACH2 */
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outl(0x05, PME_IO_BASE_ADDR + 0x33);
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/* GP31 - FAN_TACH1 */
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outl(0x05, PME_IO_BASE_ADDR + 0x34);
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/* GP32 - FAN2 */
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outl(0x04, PME_IO_BASE_ADDR + 0x35);
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/* GP33 - FAN1 */
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outl(0x04, PME_IO_BASE_ADDR + 0x36);
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/* GP34 - IRRX2 */
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outl(0x05, PME_IO_BASE_ADDR + 0x37);
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/* GP35 - IRTX2 */
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outl(0x04, PME_IO_BASE_ADDR + 0x38);
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/* GP36 - nKBDRST */
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outl(0x84, PME_IO_BASE_ADDR + 0x39);
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/* GP37 - A20M */
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outl(0x84, PME_IO_BASE_ADDR + 0x3a);
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/* GP40 - DRVDEN0 */
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outl(0x04, PME_IO_BASE_ADDR + 0x3b);
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/* GP41 - DRVDEN1 */
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outl(0x04, PME_IO_BASE_ADDR + 0x3c);
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/* GP42 - nIO_PME */
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outl(0x84, PME_IO_BASE_ADDR + 0x3d);
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/* GP43 */
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outl(0x00, PME_IO_BASE_ADDR + 0x3e);
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/* GP50 - nIR2 */
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outl(0x05, PME_IO_BASE_ADDR + 0x3f);
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/* GP51 - nDCD2 */
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outl(0x05, PME_IO_BASE_ADDR + 0x40);
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/* GP52 - RXD2 */
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outl(0x05, PME_IO_BASE_ADDR + 0x41);
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/* GP53 - TXD2 */
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outl(0x04, PME_IO_BASE_ADDR + 0x42);
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/* GP54 - nDSR2 */
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outl(0x05, PME_IO_BASE_ADDR + 0x43);
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/* GP55 - nRTS2 */
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outl(0x04, PME_IO_BASE_ADDR + 0x44);
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/* GP56 - nCTS2 */
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outl(0x05, PME_IO_BASE_ADDR + 0x45);
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/* GP57 - nDTR2 */
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outl(0x04, PME_IO_BASE_ADDR + 0x46);
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/* GP60 - LED1 */
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outl(0x84, PME_IO_BASE_ADDR + 0x47);
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/* GP61 - LED2 */
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outl(0x84, PME_IO_BASE_ADDR + 0x48);
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/* GP1 */
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outl(0x00, PME_IO_BASE_ADDR + 0x4b);
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/* GP2 */
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outl(0x14, PME_IO_BASE_ADDR + 0x4c);
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/* GP3 */
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outl(0xda, PME_IO_BASE_ADDR + 0x4d);
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/* GP4 */
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outl(0x08, PME_IO_BASE_ADDR + 0x4e);
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/* GP5 */
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outl(0x00, PME_IO_BASE_ADDR + 0x4f);
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/* GP6 */
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outl(0x00, PME_IO_BASE_ADDR + 0x50);
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/* FAN1 */
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outl(0x01, PME_IO_BASE_ADDR + 0x56);
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/* FAN2 */
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||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x57);
|
||||||
|
|
||||||
|
/* Fan Control */
|
||||||
|
outl(0xf0, PME_IO_BASE_ADDR + 0x58);
|
||||||
|
|
||||||
|
/* Fan1 Preload */
|
||||||
|
outl(0x00, PME_IO_BASE_ADDR + 0x5b);
|
||||||
|
|
||||||
|
/* Fan2 Preload */
|
||||||
|
outl(0x00, PME_IO_BASE_ADDR + 0x5c);
|
||||||
|
|
||||||
|
/* LED1 */
|
||||||
|
outl(0x03, PME_IO_BASE_ADDR + 0x5d);
|
||||||
|
|
||||||
|
/* LED2 */
|
||||||
|
outl(0x03, PME_IO_BASE_ADDR + 0x5e);
|
||||||
|
|
||||||
|
/* Keyboard Scan Code */
|
||||||
|
outl(0x00, PME_IO_BASE_ADDR + 0x5f);
|
||||||
|
|
||||||
|
/* Exit the configuration state. */
|
||||||
|
outb(0xaa, port);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,53 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch/pirq_routing.h>
|
||||||
|
|
||||||
|
const struct irq_routing_table intel_irq_routing_table = {
|
||||||
|
PIRQ_SIGNATURE, /* u32 signature */
|
||||||
|
PIRQ_VERSION, /* u16 version */
|
||||||
|
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus (7)*/
|
||||||
|
0x00, /* Interrupt router bus */
|
||||||
|
(0x1f << 3) | 0x0, /* Interrupt router dev */
|
||||||
|
0, /* IRQs devoted exclusively to PCI usage */
|
||||||
|
0x8086, /* Vendor */
|
||||||
|
0x2440, /* Device */
|
||||||
|
0, /* Miniport */
|
||||||
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||||
|
0xd9, /* Checksum (has to be set to some value that
|
||||||
|
* would give 0 after the sum of all bytes
|
||||||
|
* for this structure (including checksum).
|
||||||
|
*/
|
||||||
|
{
|
||||||
|
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||||
|
{0x00, (0x00 << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
|
||||||
|
{0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
|
||||||
|
{0x00, (0x1e << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
|
||||||
|
{0x00, (0x1f << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x6b, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0},
|
||||||
|
{0x01, (0x01 << 3) | 0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}}, 0x1, 0x0},
|
||||||
|
{0x01, (0x02 << 3) | 0x0, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}}, 0x2, 0x0},
|
||||||
|
{0x01, (0x08 << 3) | 0x0, {{0x68, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||||
|
{
|
||||||
|
return copy_pirq_routing_table(addr);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <device/device.h>
|
||||||
|
#include <boot/tables.h>
|
||||||
|
#include "chip.h"
|
||||||
|
|
||||||
|
int add_mainboard_resources(struct lb_memory *mem)
|
||||||
|
{
|
||||||
|
return add_northbridge_resources(mem);
|
||||||
|
}
|
||||||
|
|
||||||
|
struct chip_operations mainboard_ops = {
|
||||||
|
CHIP_NAME("Intel D810E2CB Mainboard")
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,67 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <stdlib.h>
|
||||||
|
#include <device/pci_def.h>
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include <device/pnp_def.h>
|
||||||
|
#include <arch/romcc_io.h>
|
||||||
|
#include <arch/hlt.h>
|
||||||
|
#include <console/console.h>
|
||||||
|
#include "lib/ramtest.c"
|
||||||
|
#include "southbridge/intel/i82801bx/i82801bx.h"
|
||||||
|
#include "southbridge/intel/i82801bx/i82801bx_early_smbus.c"
|
||||||
|
#include "northbridge/intel/i82810/raminit.h"
|
||||||
|
#include "lib/debug.c"
|
||||||
|
#include "pc80/udelay_io.c"
|
||||||
|
#include "lib/delay.c"
|
||||||
|
#include "cpu/x86/bist.h"
|
||||||
|
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
|
||||||
|
#include "gpio.c"
|
||||||
|
|
||||||
|
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
|
||||||
|
|
||||||
|
static inline int spd_read_byte(unsigned int device, unsigned int address)
|
||||||
|
{
|
||||||
|
return smbus_read_byte(device, address);
|
||||||
|
}
|
||||||
|
|
||||||
|
#include "northbridge/intel/i82810/raminit.c"
|
||||||
|
/* #include "northbridge/intel/i82810/debug.c" */
|
||||||
|
|
||||||
|
void main(unsigned long bist)
|
||||||
|
{
|
||||||
|
/* Set southbridge and superio gpios */
|
||||||
|
mb_gpio_init();
|
||||||
|
|
||||||
|
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||||
|
uart_init();
|
||||||
|
console_init();
|
||||||
|
|
||||||
|
report_bist_failure(bist);
|
||||||
|
enable_smbus();
|
||||||
|
/* dump_spd_registers(); */
|
||||||
|
sdram_set_registers();
|
||||||
|
sdram_set_spd_registers();
|
||||||
|
sdram_enable();
|
||||||
|
/* ram_check(0, 640 * 1024); */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -37,10 +37,8 @@ extern void i82801bx_enable(device_t dev);
|
||||||
#define PMBASE_ADDR 0x0400 /* ACPI Base Address Register */
|
#define PMBASE_ADDR 0x0400 /* ACPI Base Address Register */
|
||||||
#define ACPI_CNTL 0x44
|
#define ACPI_CNTL 0x44
|
||||||
#define BIOS_CNTL 0x4E
|
#define BIOS_CNTL 0x4E
|
||||||
#define GPIO_BASE_ICH0_5 0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */
|
#define GPIO_BASE 0x58 /* LPC GPIO Base Address Register */
|
||||||
#define GPIO_BASE_ICH6_9 0x48 /* LPC GPIO Base Address Register (ICH6-ICH9) */
|
#define GPIO_CNTL 0x5C /* LPC GPIO Control Register */
|
||||||
#define GPIO_CNTL_ICH0_5 0x5C /* LPC GPIO Control Register (ICH0-ICH5) */
|
|
||||||
#define GPIO_CNTL_ICH6_9 0x4C /* LPC GPIO Control Register (ICH6-ICH9) */
|
|
||||||
|
|
||||||
#define PIRQA_ROUT 0x60
|
#define PIRQA_ROUT 0x60
|
||||||
#define PIRQB_ROUT 0x61
|
#define PIRQB_ROUT 0x61
|
||||||
|
|
@ -69,6 +67,8 @@ extern void i82801bx_enable(device_t dev);
|
||||||
#define MTT 0x70
|
#define MTT 0x70
|
||||||
#define PCI_MAST_STS 0x82
|
#define PCI_MAST_STS 0x82
|
||||||
|
|
||||||
|
#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
|
||||||
|
|
||||||
#define TCOBASE 0x60 /* TCO Base Address Register */
|
#define TCOBASE 0x60 /* TCO Base Address Register */
|
||||||
#define TCO1_CNT 0x08 /* TCO1 Control Register */
|
#define TCO1_CNT 0x08 /* TCO1 Control Register */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -32,8 +32,6 @@
|
||||||
#include <arch/io.h>
|
#include <arch/io.h>
|
||||||
#include "i82801bx.h"
|
#include "i82801bx.h"
|
||||||
|
|
||||||
#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
|
|
||||||
|
|
||||||
#define NMI_OFF 0
|
#define NMI_OFF 0
|
||||||
|
|
||||||
typedef struct southbridge_intel_i82801bx_config config_t;
|
typedef struct southbridge_intel_i82801bx_config config_t;
|
||||||
|
|
@ -206,18 +204,11 @@ static void i82801bx_power_options(device_t dev)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void gpio_init(device_t dev, uint16_t ich_model)
|
static void gpio_init(device_t dev)
|
||||||
{
|
{
|
||||||
/* Set the value for GPIO base address register and enable GPIO.
|
/* Set the value for GPIO base address register and enable GPIO. */
|
||||||
* Note: ICH-ICH5 registers differ from ICH6-ICH9.
|
pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
|
||||||
*/
|
pci_write_config8(dev, GPIO_CNTL, 0x10);
|
||||||
if (ich_model <= 0x24D0) {
|
|
||||||
pci_write_config32(dev, GPIO_BASE_ICH0_5, (GPIO_BASE_ADDR | 1));
|
|
||||||
pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
|
|
||||||
} else if (ich_model >= 0x2640) {
|
|
||||||
pci_write_config32(dev, GPIO_BASE_ICH6_9, (GPIO_BASE_ADDR | 1));
|
|
||||||
pci_write_config8(dev, GPIO_CNTL_ICH6_9, 0x10);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void i82801bx_rtc_init(struct device *dev)
|
void i82801bx_rtc_init(struct device *dev)
|
||||||
|
|
@ -291,7 +282,7 @@ static void lpc_init(struct device *dev)
|
||||||
i82801bx_power_options(dev);
|
i82801bx_power_options(dev);
|
||||||
|
|
||||||
/* Set the state of the GPIO lines. */
|
/* Set the state of the GPIO lines. */
|
||||||
gpio_init(dev, ich_model);
|
gpio_init(dev);
|
||||||
|
|
||||||
/* Initialize the real time clock. */
|
/* Initialize the real time clock. */
|
||||||
i82801bx_rtc_init(dev);
|
i82801bx_rtc_init(dev);
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue