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soc/intel/xeon_sp: Add P2SB definition for SPR-SP 

Change-Id: I2ece7aac4339266068d4fc8fb1c58d0573eb2895
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This commit is contained in:
Jonathan Zhang 2023-01-30 13:24:43 -08:00 committed by Lean Sheng Tan
parent 41ed2cb20e
commit b94cc7d367
1 changed files with 8 additions and 4 deletions
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12
src/soc/intel/xeon_sp/include/soc/p2sb.h
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@ -3,14 +3,18 @@
#include <commonlib/helpers.h> #include <commonlib/helpers.h>
/* /*
* Currently all known xeon-sp CPUs use C620 PCH. These definitions * CPX-SP and SKX-SP use LBG PCH, while SPR-SP uses EBG PCH.
* come from C620 datasheet (Intel Doc #336067-007US) * These definitions come from LBG datasheet (Intel Doc #336067-007US)
* and Emmitsburg datasheet (Intel Doc #606161).
*/ */
#define HPTC_OFFSET 0x60 #define HPTC_OFFSET 0x60
#define HPTC_ADDR_ENABLE_BIT (1 << 7) #define HPTC_ADDR_ENABLE_BIT (1 << 7)
#define PCH_P2SB_EPMASK0 0xb0
#define P2SB_SIZE (16 * MiB) #define P2SB_SIZE (16 * MiB)
#define P2SBC 0xe0 #define P2SBC 0xe0
#define SBILOCK (1 << 31) #define SBILOCK (1 << 31)
#if CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP)
#define PCH_P2SB_EPMASK0 0x220
#else
#define PCH_P2SB_EPMASK0 0xb0
#endif