diff --git a/src/soc/amd/sabrina/fch.c b/src/soc/amd/sabrina/fch.c
index 9be7dd8912..a768989b64 100644
--- a/src/soc/amd/sabrina/fch.c
+++ b/src/soc/amd/sabrina/fch.c
@@ -127,11 +127,6 @@ static void fch_init_acpi_ports(void)
 				PM_ACPI_TIMER_EN_EN);
 }
 
-static void fch_init_resets(void)
-{
-	pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD);
-}
-
 /* configure the general purpose PCIe clock outputs according to the devicetree settings */
 static void gpp_clk_setup(void)
 {
@@ -198,7 +193,6 @@ static void cgpll_clock_gate_init(void)
 
 void fch_init(void *chip_info)
 {
-	fch_init_resets();
 	i2c_soc_init();
 	fch_init_acpi_ports();
 
diff --git a/src/soc/amd/sabrina/reset.c b/src/soc/amd/sabrina/reset.c
index 90fedda904..28e60b6307 100644
--- a/src/soc/amd/sabrina/reset.c
+++ b/src/soc/amd/sabrina/reset.c
@@ -19,9 +19,7 @@ void do_cold_reset(void)
 
 void do_warm_reset(void)
 {
-	/* Warm resets are not supported and must be executed as cold */
-	pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
-		TOGGLE_ALL_PWR_GOOD);
+	/* Assert reset signals only. */
 	outb(RST_CPU | SYS_RST, RST_CNT);
 }