soc/cavium/common: Make ecam0_get_bar_val common

Move ecam0_get_bar_val into the common folder and make it public.
Compile it for romstage and ramstage.

To be used by romstage PCI code.
Tested on OpenCellular Elgon.

Change-Id: I18b1ede56795bf8c1f9476592291b8ea610eccd4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

src/soc/cavium/cn81xx/ecam0.c

@@ -22,6 +22,7 @@
 #include <device/pci_ops.h>
 #include <soc/addressmap.h>
 #include <soc/cavium/common/pci/chip.h>
+#include <soc/ecam.h>
 #include <assert.h>
 
 #define CAVM_PCCPF_XXX_VSEC_CTL 0x108
@@ -136,50 +137,6 @@ static void ecam0_fix_missing_devices(struct bus *link)
 	}
 }
 
-/**
- * Get PCI BAR address from cavium specific extended capability.
- * Use regular BAR if not found in extended capability space.
- *
- * @return The pyhsical address of the BAR, zero on error
- */
-static uint64_t get_bar_val(struct device *dev, u8 bar)
-{
-	size_t cap_offset = pci_find_capability(dev, 0x14);
-	uint64_t h, l, ret = 0;
-	if (cap_offset) {
-		/* Found EA */
-		u8 es, bei;
-		u8 ne = pci_read_config8(dev, cap_offset + 2) & 0x3f;
-
-		cap_offset += 4;
-		while (ne) {
-			uint32_t dw0 = pci_read_config32(dev, cap_offset);
-
-			es = dw0 & 7;
-			bei = (dw0 >> 4) & 0xf;
-			if (bei == bar) {
-				h = 0;
-				l = pci_read_config32(dev, cap_offset + 4);
-				if (l & 2)
-					h = pci_read_config32(dev,
-							      cap_offset + 12);
-				ret = (h << 32) | (l & ~0xfull);
-				break;
-			}
-			cap_offset += (es + 1) * 4;
-			ne--;
-		}
-	} else {
-		h = 0;
-		l = pci_read_config32(dev, bar * 4 + PCI_BASE_ADDRESS_0);
-		if (l & 4)
-			h = pci_read_config32(dev, bar * 4 + PCI_BASE_ADDRESS_0
-					      + 4);
-		ret = (h << 32) | (l & ~0xfull);
-	}
-	return ret;
-}
-
 /**
  * pci_enable_msix - configure device's MSI-X capability structure
  * @dev: pointer to the pci_dev data structure of MSI-X device function
@@ -237,7 +194,7 @@ static size_t ecam0_pci_enable_msix(struct device *dev,
 		       dev_path(dev));
 		return -1;
 	}
-	bar = get_bar_val(dev, bar_idx);
+	bar = ecam0_get_bar_val(dev, bar_idx);
 	if (!bar) {
 		printk(BIOS_ERR, "ERROR: %s: Failed to find MSI-X bar\n",
 		       dev_path(dev));

src/soc/cavium/common/Makefile.inc

@@ -25,11 +25,13 @@ bootblock-$(CONFIG_BOOTBLOCK_CUSTOM) += bootblock.c
 # romstage
 
 romstage-y += bdk-coreboot.c
+romstage-y += ecam.c
 
 ################################################################################
 # ramstage
 
 ramstage-y += bdk-coreboot.c
+ramstage-y += ecam.c
 
 CPPFLAGS_common += -Isrc/soc/cavium/common/include
 

src/soc/cavium/common/ecam.c

@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018       Facebook, Inc.
+ * Copyright 2003-2017  Cavium Inc.  <support@cavium.com>
+ * Copyright 2019       9elements Agency GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0.
+ */
+
+#include <arch/io.h>
+#include <device/pci_ops.h>
+#include <device/pci_def.h>
+#include <device/pci.h>
+#include <soc/addressmap.h>
+#include <soc/ecam.h>
+#include <assert.h>
+
+/**
+ * Get PCI BAR address from cavium specific extended capability.
+ * Use regular BAR if not found in extended capability space.
+ *
+ * @return The pyhsical address of the BAR, zero on error
+ */
+#ifdef __SIMPLE_DEVICE__
+uint64_t ecam0_get_bar_val(pci_devfn_t dev, u8 bar)
+#else
+uint64_t ecam0_get_bar_val(struct device *dev, u8 bar)
+#endif
+{
+	size_t cap_offset = pci_find_capability(dev, 0x14);
+	uint64_t h, l, ret = 0;
+	if (cap_offset) {
+		/* Found EA */
+		u8 es, bei;
+		u8 ne = pci_read_config8(dev, cap_offset + 2) & 0x3f;
+
+		cap_offset += 4;
+		while (ne) {
+			uint32_t dw0 = pci_read_config32(dev, cap_offset);
+
+			es = dw0 & 7;
+			bei = (dw0 >> 4) & 0xf;
+			if (bei == bar) {
+				h = 0;
+				l = pci_read_config32(dev, cap_offset + 4);
+				if (l & 2)
+					h = pci_read_config32(dev,
+							      cap_offset + 12);
+				ret = (h << 32) | (l & ~0xfull);
+				break;
+			}
+			cap_offset += (es + 1) * 4;
+			ne--;
+		}
+	} else {
+		h = 0;
+		l = pci_read_config32(dev, bar * 4 + PCI_BASE_ADDRESS_0);
+		if (l & 4)
+			h = pci_read_config32(dev, bar * 4 + PCI_BASE_ADDRESS_0
+					      + 4);
+		ret = (h << 32) | (l & ~0xfull);
+	}
+	return ret;
+}

src/soc/cavium/common/include/soc/ecam.h

@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018-present Facebook, Inc.
+ * Copyright 2019         9elements Agency GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_ECAM_H
+#define __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_ECAM_H
+
+#ifdef __SIMPLE_DEVICE__
+#include <device/pci_type.h>
+
+uint64_t ecam0_get_bar_val(pci_devfn_t dev, u8 bar);
+#else
+#include <device/device.h>
+
+uint64_t ecam0_get_bar_val(struct device *dev, u8 bar);
+#endif
+
+#endif