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fsp_baytrail: Add additional PCI space above 4GB 

This just tells the OS that it can use the 16GB of address space
at the 48GB mark for PCI.  This is the upper 16GB of Bay Trail's 36 bit
physical address space.

This could be hardcoded into the UMEM definition, but doing it this way
makes it more plain what it's doing, and allows for modification
to put it just above the top of upper memory, similar to what is done
with the standard PCI region above the top of low memory.

Change-Id: Id6208c3712e5d94d62a83c4ac69e8ffd0e19f4ad
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12791
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: York Yang <york.yang@intel.com>
This commit is contained in:
Martin Roth 2015-12-22 12:40:53 -07:00
parent 481a19cf99
commit b95a074586
1 changed files with 15 additions and 0 deletions
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15
src/soc/intel/fsp_baytrail/acpi/southcluster.asl
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@ -163,6 +163,12 @@ Name (MCRS, ResourceTemplate()
Cacheable, ReadWrite, Cacheable, ReadWrite,
0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
0x00005000,,, TPMR) 0x00005000,,, TPMR)
// High PCI Memory Region
QwordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000,,, UMEM)
}) })
Method (_CRS, 0, Serialized) Method (_CRS, 0, Serialized)
@ -177,6 +183,15 @@ Method (_CRS, 0, Serialized)
Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
Add (Subtract (PMAX, PMIN), 1, PLEN) Add (Subtract (PMAX, PMIN), 1, PLEN)
// Update High PCI resource area
CreateQwordField(MCRS, ^UMEM._MIN, UMIN)
CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
Store(0x40000000 * 48, UMIN) // Set base address to 48GB
Store(0x40000000 * 16, ULEN) // Allocate 16GB for PCI space
Add(UMIN, Subtract(ULEN, 1), UMAX)
Return (MCRS) Return (MCRS)
} }