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mb/intel/adlrvp: remove I2S2 GPIO settings 

It turns out that there is no device connected to I2S2.
This patch clarifies the GPIO settings device association and remove
unnecessary configuration.

GPP_A8  -> default: GP-in ; set to NF1: SRCCLKREQ7#
GPP_A9  -> default: NF1: ESPI_CLK
GPP_A10 -> default: NF1: ESPI_RESET#

BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I7a575f495d841fe0bf6fd86a84caeee064f6904b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This commit is contained in:
Cliff Huang 2022-06-28 17:18:17 -07:00 committed by Felix Held
parent 59e03ebf4c
commit b95a821576
1 changed files with 5 additions and 7 deletions
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12
src/mainboard/intel/adlrvp/gpio.c
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@ -7,6 +7,10 @@
/* Pad configuration in ramstage */ /* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
/* GPIO A0-A6, A9-A10 default function is NF1 for eSPI interface when
eSPI is enabled */
/* SSD1_PWREN CPU SSD1 */ /* SSD1_PWREN CPU SSD1 */
PAD_CFG_GPO(GPP_D14, 1, PLTRST), PAD_CFG_GPO(GPP_D14, 1, PLTRST),
/* SSD1_RESET CPU SSD1 */ /* SSD1_RESET CPU SSD1 */
@ -187,13 +191,6 @@ static const struct pad_config gpio_table[] = {
/* I2S0_RXD */ /* I2S0_RXD */
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
/* I2S2_SFRM */
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
/* I2S2_TXD */
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
/* I2S2_RXD */
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
/* I2S_MCLK1_OUT */ /* I2S_MCLK1_OUT */
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
/* I2S_MCLK2_INOUT */ /* I2S_MCLK2_INOUT */
@ -240,6 +237,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_D8, NONE), PAD_NC(GPP_D8, NONE),
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
/* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */ /* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),