mb/google/brask/var/kuldax: add fw_config and enable BT offload
add fw_config probe for auido and enable BT offload support. BUG=b:232419816 b:232419765 TEST=FW_NAME=kuldax emerge-brask coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Id58e48cc2510d0377040d86bb9dbbb45bec7d624 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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@ -4,3 +4,5 @@ bootblock-y += gpio.c
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romstage-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
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ramstage-$(CONFIG_FW_CONFIG) += variant.c
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@ -0,0 +1,75 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootstate.h>
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#include <console/console.h>
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#include <fw_config.h>
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#include <gpio.h>
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static const struct pad_config dmic_enable_pads[] = {
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PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */
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PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */
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};
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static const struct pad_config dmic_disable_pads[] = {
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PAD_NC(GPP_R6, NONE),
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PAD_NC(GPP_R7, NONE),
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};
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static const struct pad_config i2s_enable_pads[] = {
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */
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PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */
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PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */
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PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */
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};
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static const struct pad_config i2s_disable_pads[] = {
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PAD_NC(GPP_R0, NONE),
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PAD_NC(GPP_R1, NONE),
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PAD_NC(GPP_R2, NONE),
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PAD_NC(GPP_R3, NONE),
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};
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static const struct pad_config bt_i2s_enable_pads[] = {
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PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */
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PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */
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PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */
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PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */
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PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */
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PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */
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PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */
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PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */
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};
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static const struct pad_config bt_i2s_disable_pads[] = {
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PAD_NC(GPP_VGPIO_30, NONE),
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PAD_NC(GPP_VGPIO_31, NONE),
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PAD_NC(GPP_VGPIO_32, NONE),
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PAD_NC(GPP_VGPIO_33, NONE),
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PAD_NC(GPP_VGPIO_34, NONE),
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PAD_NC(GPP_VGPIO_35, NONE),
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PAD_NC(GPP_VGPIO_36, NONE),
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PAD_NC(GPP_VGPIO_37, NONE),
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};
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static void fw_config_handle(void *unused)
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{
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if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
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printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
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gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
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gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
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gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
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return;
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}
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if (fw_config_probe(FW_CONFIG(AUDIO, NAU88L25B_I2S))) {
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printk(BIOS_INFO, "Configure audio over I2S with NAU88L25B.\n");
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gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
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gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
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printk(BIOS_INFO, "BT offload enabled\n");
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gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
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} else {
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printk(BIOS_INFO, "BT offload disabled\n");
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gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
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}
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
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@ -1,3 +1,10 @@
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fw_config
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field AUDIO 0 2
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option AUDIO_UNKNOWN 0
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option NAU88L25B_I2S 1
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end
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end
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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register "serial_io_gspi_mode" = "{
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register "serial_io_gspi_mode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
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@ -126,7 +133,9 @@ chip soc/intel/alderlake
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register "short_key_debounce" = "2" # 100ms
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register "short_key_debounce" = "2" # 100ms
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register "jack_insert_debounce" = "7" # 512ms
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register "jack_insert_debounce" = "7" # 512ms
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register "jack_eject_debounce" = "7" # 512ms
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register "jack_eject_debounce" = "7" # 512ms
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device i2c 1a on end
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device i2c 1a on
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probe AUDIO NAU88L25B_I2S
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end
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end
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end
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end
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end
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device ref pcie_rp7 on
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device ref pcie_rp7 on
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@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <chip.h>
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#include <fw_config.h>
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#include <baseboard/variants.h>
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void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
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{
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config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
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NAU88L25B_I2S));
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}
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