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soc/amd: Make espi_clear_decodes private

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espi_setup already clears most of the controller registers. So this
change consolidates the clear logic into one spot.

This shouldn't result in a behavior change on Picasso. Picasso already
has the eSPI decodes clear on boot, so this change is a nop.

BUG=b:183524609
TEST=Boot guybrush to the OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Raul E Rangel 2021-04-02 13:47:09 -06:00 committed by Raul Rangel
parent 61ac1bc530
commit b95f848766
3 changed files with 3 additions and 11 deletions
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4
src/soc/amd/cezanne/early_fch.c
View file

@ -67,8 +67,6 @@ void fch_early_init(void)
if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
lpc_disable_spi_rom_sharing();
if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
espi_clear_decodes();
if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
espi_setup();
}
}

7
src/soc/amd/common/block/include/amdblocks/espi.h
View file

@ -100,13 +100,6 @@ int espi_open_io_window(uint16_t base, size_t size);
*/
int espi_open_mmio_window(uint32_t base, size_t size);
/*
* Clear all configured eSPI memory and I/O decode ranges. This is useful for changing
* the decodes, or if something else has previously setup decode windows that conflict
* with the windows that coreboot needs.
*/
void espi_clear_decodes(void);
/*
* In cases where eSPI BAR is statically provided by SoC, use that BAR instead of reading
* SPIBASE. This is required for cases where verstage runs on PSP.

3
src/soc/amd/common/block/lpc/espi_util.c
View file

@ -98,7 +98,7 @@ static int espi_get_unused_io_window(void)
return -1;
}
void espi_clear_decodes(void)
static void espi_clear_decodes(void)
{
unsigned int idx;
@ -894,6 +894,7 @@ int espi_setup(void)
espi_write32(ESPI_GLOBAL_CONTROL_1, ESPI_RGCMD_INT(23) | ESPI_ERR_INT_SMI);
espi_write32(ESPI_SLAVE0_INT_EN, 0);
espi_clear_status();
espi_clear_decodes();
/*
* Boot sequence: Step 1