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nb/intel/haswell/bootblock.c: include <arch/pci_io_cfg.h> 

Also rename 'reg' to 'reg32'.

Change-Id: Ie8dd238a8f10daad9653f44b3ada329c3ede58fe
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes HAOUAS 2021-01-31 08:27:35 +01:00 committed by Patrick Georgi
parent 9cbf26d18e
commit b96c358751
1 changed files with 4 additions and 3 deletions
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7
src/northbridge/intel/haswell/bootblock.c
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@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/bootblock.h> #include <arch/bootblock.h>
#include <arch/pci_io_cfg.h>
#include <assert.h> #include <assert.h>
#include <device/pci_ops.h>
#include <types.h> #include <types.h>
#include "haswell.h" #include "haswell.h"
static uint32_t encode_pciexbar_length(void) static uint32_t encode_pciexbar_length(void)
@ -28,7 +29,7 @@ void bootblock_early_northbridge_init(void)
* *
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/ */
const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
} }