cpu/intel/model_206ax: Use tsc monotonic timer

Switch from lapic to tsc.

Allows timestamps to be used in coreboot, as there's a reference
clock available to calculate correct time units.

Clean Kconfig, remove duplicated lapic code and include tsc dir for
LGA1155 boards.

Tested on Lenovo T430.

Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/cpu/intel/model_206ax/Kconfig

@@ -14,12 +14,13 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_RAMSTAGE_X86_32
 	select SMP
 	select SSE2
-	select UDELAY_LAPIC
+	select UDELAY_TSC
+	select TSC_CONSTANT_RATE
+	select TSC_MONOTONIC_TIMER
 	select SMM_TSEG
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	#select AP_IN_SIPI_WAIT
 	select TSC_SYNC_MFENCE
-	select LAPIC_MONOTONIC_TIMER
 	select CPU_INTEL_COMMON
 
 config BOOTBLOCK_CPU_INIT

src/cpu/intel/model_206ax/Makefile.inc

@@ -5,6 +5,10 @@ subdirs-y += ../common
 
 ramstage-y += acpi.c
 
+ramstage-y += tsc_freq.c
+romstage-y += tsc_freq.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
+
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin

src/cpu/intel/model_206ax/tsc_freq.c

@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include "model_206ax.h"
+
+unsigned long tsc_freq_mhz(void)
+{
+	msr_t platform_info;
+
+	platform_info = rdmsr(MSR_PLATFORM_INFO);
+	return SANDYBRIDGE_BCLK * ((platform_info.lo >> 8) & 0xff);
+}

src/cpu/intel/socket_LGA1155/Makefile.inc

@@ -1,3 +1,4 @@
+subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache

src/mainboard/gigabyte/ga-b75m-d3h/Kconfig

@@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_RESUME
 	select HAVE_SMI_HANDLER
 	select INTEL_INT15
-	select UDELAY_TSC
 	select SERIRQ_CONTINUOUS_MODE
 	select MAINBOARD_HAS_LIBGFXINIT
 	select MAINBOARD_HAS_LPC_TPM

src/mainboard/gigabyte/ga-b75m-d3v/Kconfig

@@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_RESUME
 	select HAVE_SMI_HANDLER
 	select INTEL_INT15
-	select UDELAY_TSC
 	select SERIRQ_CONTINUOUS_MODE
 
 config MMCONF_BASE_ADDRESS

src/mainboard/sapphire/pureplatinumh61/Kconfig

@@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_RESUME
 	select MAINBOARD_HAS_LIBGFXINIT
 	select INTEL_INT15
-	select UDELAY_TSC
 	select SERIRQ_CONTINUOUS_MODE
 
 config HAVE_IFD_BIN

src/northbridge/intel/fsp_sandybridge/Makefile.inc

@@ -29,7 +29,6 @@ romstage-y += early_init.c
 romstage-y += report_platform.c
 romstage-y += ../../../arch/x86/walkcbfs.S
 
-smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
 CPPFLAGS_common += -I$(src)/northbridge/intel/fsp_sandybridge/fsp

src/northbridge/intel/fsp_sandybridge/udelay.c

@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <delay.h>
-#include <stdint.h>
-#include <cpu/x86/tsc.h>
-#include <cpu/x86/msr.h>
-
-/**
- * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK = 100MHz
- */
-
-void udelay(u32 us)
-{
-	u32 dword;
-	tsc_t tsc, tsc1, tscd;
-	msr_t msr;
-	u32 fsb = 100, divisor;
-	u32 d;			/* ticks per us */
-
-	msr = rdmsr(0xce);
-	divisor = (msr.lo >> 8) & 0xff;
-
-	d = fsb * divisor; /* On Core/Core2 this is divided by 4 */
-	multiply_to_tsc(&tscd, us, d);
-
-	tsc1 = rdtsc();
-	dword = tsc1.lo + tscd.lo;
-	if ((dword < tsc1.lo) || (dword < tscd.lo)) {
-		tsc1.hi++;
-	}
-	tsc1.lo = dword;
-	tsc1.hi += tscd.hi;
-
-	do {
-		tsc = rdtsc();
-	} while ((tsc.hi < tsc1.hi)
-		 || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo)));
-}

src/northbridge/intel/sandybridge/Makefile.inc

@@ -43,7 +43,6 @@ romstage-y += early_init.c
 romstage-y += report_platform.c
 romstage-y += ../../../arch/x86/walkcbfs.S
 
-smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
 ifneq ($(CONFIG_CHROMEOS),y)

src/northbridge/intel/sandybridge/udelay.c

@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <delay.h>
-#include <stdint.h>
-#include <cpu/x86/tsc.h>
-#include <cpu/x86/msr.h>
-
-/**
- * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz
- */
-
-void udelay(u32 us)
-{
-	u32 dword;
-	tsc_t tsc, tsc1, tscd;
-	msr_t msr;
-	u32 fsb = 100, divisor;
-	u32 d;			/* ticks per us */
-
-	msr = rdmsr(0xce);
-	divisor = (msr.lo >> 8) & 0xff;
-
-	d = fsb * divisor;	/* On Core/Core2 this is divided by 4 */
-	multiply_to_tsc(&tscd, us, d);
-
-	tsc1 = rdtsc();
-	dword = tsc1.lo + tscd.lo;
-	if ((dword < tsc1.lo) || (dword < tscd.lo)) {
-		tsc1.hi++;
-	}
-	tsc1.lo = dword;
-	tsc1.hi += tscd.hi;
-
-	do {
-		tsc = rdtsc();
-	} while ((tsc.hi < tsc1.hi)
-		 || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
-}
-
-#if CONFIG_LAPIC_MONOTONIC_TIMER && !defined(__PRE_RAM__)
-#include <timer.h>
-
-void timer_monotonic_get(struct mono_time *mt)
-{
-	tsc_t tsc;
-	msr_t msr;
-	u32 fsb = 100, divisor;
-	u32 d;			/* ticks per us */
-
-	msr = rdmsr(0xce);
-	divisor = (msr.lo >> 8) & 0xff;
-	d = fsb * divisor;	/* On Core/Core2 this is divided by 4 */
-
-	tsc = rdtsc();
-
-	mt->microseconds = (long)((((uint64_t)tsc.hi << 32) | tsc.lo) / d);
-}
-#endif